C8051F960-A-GQ Silicon Labs, C8051F960-A-GQ Datasheet - Page 447
![no-image](/images/no-image-200.jpg)
C8051F960-A-GQ
Manufacturer Part Number
C8051F960-A-GQ
Description
8-bit Microcontrollers - MCU 128KB DC-DC LCD AES
Manufacturer
Silicon Labs
Datasheet
1.C8051F960-A-GQ.pdf
(492 pages)
Specifications of C8051F960-A-GQ
Rohs
yes
Core
8051
Processor Series
C8051
Data Bus Width
8 bit
Maximum Clock Frequency
24.5 MHz
Program Memory Size
128 KB
Data Ram Size
8 KB
On-chip Adc
Yes
Operating Supply Voltage
1.8 V to 3.8 V
Operating Temperature Range
- 40 C to + 85 C
Package / Case
QFP-80
Mounting Style
SMD/SMT
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F960-A-GQ
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
Company:
Part Number:
C8051F960-A-GQR
Manufacturer:
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32.1.2. Mode 1: 16-bit Counter/Timer
Mode 1 operation is the same as Mode 0, except that the counter/timer registers use all 16 bits. The coun-
ter/timers are enabled and configured in Mode 1 in the same manner as for Mode 0.
32.1.3. Mode 2: 8-bit Counter/Timer with Auto-Reload
Mode 2 configures Timer 0 and Timer 1 to operate as 8-bit counter/timers with automatic reload of the start
value. TL0 holds the count and TH0 holds the reload value. When the counter in TL0 overflows from all
ones to 0x00, the timer overflow flag TF0 (TCON.5) is set and the counter in TL0 is reloaded from TH0. If
Timer 0 interrupts are enabled, an interrupt will occur when the TF0 flag is set. The reload value in TH0 is
not changed. TL0 must be initialized to the desired value before enabling the timer for the first count to be
correct. When in Mode 2, Timer 1 operates identically to Timer 0.
Both counter/timers are enabled and configured in Mode 2 in the same manner as Mode 0. Setting the
TR0 bit (TCON.4) enables the timer when either GATE0 (TMOD.3) is logic 0 or when the input signal INT0
is active as defined by bit IN0PL in register IT01CF (see Section “17.6. External Interrupts INT0 and INT1”
on page 242 for details on the external input signals INT0 and INT1).
IN T 0
T 0
C ro ss b a r
P re -s ca le d C lo c k
S Y S C L K
IN 0 P L
G A T E 0
X O R
Figure 32.1. T0 Mode 0 Block Diagram
T R 0
0
1
M
H
T
3
M
T
3
L
C K C O N
M
H
T
2
M
T
2
L
0
1
M
T
1
M
T
0
S
C
A
1
S
C
A
0
Rev. 0.5
G
A
T
E
1
C
T
1
/
M
T
1
1
T M O D
M
T
1
0
T C L K
G
A
E
T
0
C
T
0
/
M
T
0
1
M
T
0
0
(5 b its )
T L 0
N
1
P
L
I
N
1
S
L
2
I
IT 0 1 C F
N
1
S
L
1
I
N
1
S
L
0
I
N
P
0
L
I
(8 b its)
T H 0
N
S
0
L
2
I
N
S
0
L
1
I
N
S
0
L
0
I
C8051F96x
T R 1
T R 0
T F 1
T F 0
IE 1
IE 0
IT 1
IT 0
Inte rru pt
447
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