C8051F960-A-GQ Silicon Labs, C8051F960-A-GQ Datasheet - Page 403
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C8051F960-A-GQ
Manufacturer Part Number
C8051F960-A-GQ
Description
8-bit Microcontrollers - MCU 128KB DC-DC LCD AES
Manufacturer
Silicon Labs
Datasheet
1.C8051F960-A-GQ.pdf
(492 pages)
Specifications of C8051F960-A-GQ
Rohs
yes
Core
8051
Processor Series
C8051
Data Bus Width
8 bit
Maximum Clock Frequency
24.5 MHz
Program Memory Size
128 KB
Data Ram Size
8 KB
On-chip Adc
Yes
Operating Supply Voltage
1.8 V to 3.8 V
Operating Temperature Range
- 40 C to + 85 C
Package / Case
QFP-80
Mounting Style
SMD/SMT
Available stocks
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Quantity
Price
Company:
Part Number:
C8051F960-A-GQ
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
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Part Number:
C8051F960-A-GQR
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29.1. Enhanced Baud Rate Generation
The UART0 baud rate is generated by Timer 1 in 8-bit auto-reload mode. The TX clock is generated by
TL1; the RX clock is generated by a copy of TL1 (shown as RX Timer in Figure 29.2), which is not user-
accessible. Both TX and RX Timer overflows are divided by two to generate the TX and RX baud rates.
The RX Timer runs when Timer 1 is enabled, and uses the same reload value (TH1). However, an
RX Timer reload is forced when a START condition is detected on the RX pin. This allows a receive to
begin any time a START is detected, independent of the TX Timer state.
Timer 1 should be configured for Mode 2, 8-bit auto-reload (see Section “32.1.3. Mode 2: 8-bit Coun-
ter/Timer with Auto-Reload” on page 447). The Timer 1 reload value should be set so that overflows will
occur at two times the desired UART baud rate frequency. Note that Timer 1 may be clocked by one of six
sources: SYSCLK, SYSCLK / 4, SYSCLK / 12, SYSCLK / 48, the external oscillator clock / 8, or an exter-
nal input T1. For any given Timer 1 clock source, the UART0 baud rate is determined by Equation -A and
Equation -B.
UART0 Baud Rate
Where T1
value). Timer 1 clock frequency is selected as described in Section “32.1. Timer 0 and Timer 1” on
page 446. A quick reference for typical baud rates and system clock frequencies is given in Table 29.1
through Table 29.2. Note that the internal oscillator may still generate the system clock when the external
oscillator is driving Timer 1.
CLK
is the frequency of the clock supplied to Timer 1, and T1H is the high byte of Timer 1 (reload
Detected
Start
A)
B)
UartBaudRate
T1_Overflow_Rate
Figure 29.2. UART0 Baud Rate Logic
RX Timer
Timer 1
TH1
TL1
=
Overflow
Overflow
Rev. 0.5
1
-- -
2
=
T1_Overflow_Rate
------------------------- -
256 TH1
T1
–
CLK
2
2
UART
RX Clock
TX Clock
C8051F96x
403
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