ATSAM3X4EA-AU Atmel, ATSAM3X4EA-AU Datasheet - Page 334

• Manufacturer Part Number: ATSAM3X4EA-AU
• Description: ARM Microcontrollers - MCU QFP144,GREEN, IND TEMP, MRL A
• Manufacturer: Atmel

Specifications of ATSAM3X4EA-AU

• Rohs: yes
• Core: ARM Cortex M3
• Processor Series: SAM3X
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 84 MHz
• Program Memory Size: 256 KB
• Data Ram Size: 64 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 2.4 V to 3.6 V
• Operating Temperature Range: - 40 C to +85 C
• Package / Case: LQFP-144
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 60

23.2.3
Table 23-3.
23.3
23.4
23.4.1
334
334
Slaves
0
1
2
3
4
5
6
7
8
Internal SRAM0
Internal SRAM1
Internal ROM
Internal Flash
USB High Speed Dual Port RAM
Nand Flash Controller RAM
External Bus Interface
High Speed Peripheral Bridge
Low Speed Peripheral Bridge
Memory Mapping
Special Bus Granting Techniques
SAM3X/A
SAM3X/A
Master to Slave Access
No Default Master
SAM3A/X series Master to Slave Access
All the Masters can normally access all the Slaves. However, some paths do not make sense,
for example allowing access from the USB High speed DMA to the Internal Peripherals. Thus,
these paths are forbidden or simply not wired, and shown as “-” in the following table.
Bus Matrix provides one decoder for every AHB Master Interface. The decoder offers each AHB
Master several memory mappings. In fact, depending on the product, each memory area may be
assigned to several slaves. Booting at the same address while using different AHB slaves (i.e.
internal ROM or internal Flash) becomes possible.
The Bus Matrix user interface provides Master Remap Control Register (MATRIX_MRCR) that
allows to perform remap action for every master independently.
The Bus Matrix provides some speculative bus granting techniques in order to anticipate access
requests from some masters. This mechanism allows to reduce latency at first accesses of a
burst or single transfer. The bus granting mechanism allows to set a default master for every
slave.
At the end of the current access, if no other request is pending, the slave remains connected to
its associated default master. A slave can be associated with three kinds of default masters: no
default master, last access master and fixed default master.
At the end of the current access, if no other request is pending, the slave is disconnected from
all masters. No Default Master suits low power mode.
Masters
Cortex-M3
I/D Bus
X
X
0
-
-
-
-
-
-
-
Cortex-M3 S
Bus
X
X
X
X
X
X
X
1
-
-
PDC
X
X
X
X
X
X
2
-
-
-
Speed DMA
USB High
X
X
X
X
X
3
-
-
-
-
Controller
DMA
11057B–ATARM–28-May-12
11057B–ATARM–28-May-12
X
X
X
X
X
X
X
X
4
-
EMAC
DMA
X
X
X
X
X
5
-
-
-
-