ATSAM3X4EA-AU Atmel, ATSAM3X4EA-AU Datasheet - Page 786
ATSAM3X4EA-AU
Manufacturer Part Number
ATSAM3X4EA-AU
Description
ARM Microcontrollers - MCU QFP144,GREEN, IND TEMP, MRL A
Manufacturer
Atmel
Datasheet
1.ATSAM3X8EA-AU.pdf
(1467 pages)
Specifications of ATSAM3X4EA-AU
Rohs
yes
Core
ARM Cortex M3
Processor Series
SAM3X
Data Bus Width
32 bit
Maximum Clock Frequency
84 MHz
Program Memory Size
256 KB
Data Ram Size
64 KB
On-chip Adc
Yes
Operating Supply Voltage
2.4 V to 3.6 V
Operating Temperature Range
- 40 C to +85 C
Package / Case
LQFP-144
Mounting Style
SMD/SMT
Factory Pack Quantity
60
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36.7.1.2
Figure 36-4. Fractional Baud Rate Generator
36.7.1.3
786
786
SCK
Reserved
MCK/DIV
SAM3X/A
SAM3X/A
MCK
Fractional Baud Rate in Asynchronous Mode
Baud Rate in Synchronous Mode or SPI Mode
USCLKS
0
1
2
3
The Baud Rate generator previously defined is subject to the following limitation: the output fre-
quency changes by only integer multiples of the reference frequency. An approach to this
problem is to integrate a fractional N clock generator that has a high resolution. The generator
architecture is modified to obtain Baud Rate changes by a fraction of the reference source clock.
This fractional part is programmed with the FP field in the Baud Rate Generator Register
(US_BRGR). If FP is not 0, the fractional part is activated. The resolution is one eighth of the
clock divider. This feature is only available when using USART normal mode. The fractional
Baud Rate is calculated using the following formula:
The modified architecture is presented below:
If the USART is programmed to operate in synchronous mode, the selected clock is simply
divided by the field CD in US_BRGR.
In synchronous mode, if the external clock is selected (USCLKS = 3), the clock is provided
directly by the signal on the USART SCK pin. No division is active. The value written in
US_BRGR has no effect. The external clock frequency must be at least 3 times lower than the
Baudrate
BaudRate
16-bit Counter
CD
=
---------------------------------------------------------------- -
8 2 Over
Modulus
=
Control
FP
SelectedClock
------------------------------------- -
SelectedClock
–
CD
CD
glitch-free
USCLKS = 3
+
logic
FP
------ -
FP
8
SYNC
0
CD
>1
1
0
1
0
OVER
Sampling
Divider
FIDI
11057B–ATARM–28-May-12
11057B–ATARM–28-May-12
0
1
SYNC
SCK
Baud Rate
Sampling
Clock
Clock
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