ATSAM3X4EA-AU Atmel, ATSAM3X4EA-AU Datasheet - Page 818

• Manufacturer Part Number: ATSAM3X4EA-AU
• Description: ARM Microcontrollers - MCU QFP144,GREEN, IND TEMP, MRL A
• Manufacturer: Atmel

Specifications of ATSAM3X4EA-AU

• Rohs: yes
• Core: ARM Cortex M3
• Processor Series: SAM3X
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 84 MHz
• Program Memory Size: 256 KB
• Data Ram Size: 64 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 2.4 V to 3.6 V
• Operating Temperature Range: - 40 C to +85 C
• Package / Case: LQFP-144
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 60

36.7.8.8
Figure 36-43. Slave Node Synchronization
818
818
Fractional Part (FP)
Fractional Part (FP)
Clcok Divider (CD)
Clcok Divider (CD)
Synchro Counter
US_LINBRR
US_LINBRR
US_BRGR
US_BRGR
LINIDRX
SAM3X/A
SAM3X/A
Clock
RXD
Slave Node Synchronization
The synchronization is done only in Slave node configuration. The procedure is based on time
measurement between falling edges of the Synch Field. The falling edges are available in dis-
tances of 2, 4, 6 and 8 bit times.
Figure 36-42. Synch Field
The time measurement is made by a 19-bit counter clocked by the sampling clock (see
36.7.1).
When the start bit of the Synch Field is detected, the counter is reset. Then during the next
8 Tbits of the Synch Field, the counter is incremented. At the end of these 8 Tbits, the counter is
stopped. At this moment, the 16 most significant bits of the counter (value divided by 8) give the
new clock divider (LINCD) and the 3 least significant bits of this value (the remainder) give the
new fractional part (LINFP).
When the Synch Field has been received, the clock divider (CD) and the fractional part (FP) are
updated in the Baud Rate Generator register (US_BRGR).
If it appears that the sampled Synch character is not equal to 0x55, then the error flag LINISFE
in the Channel Status register (US_CSR) is set to 1. It is reset by writing bit RSTSTA to 1 in the
Control register (US_CR).
The accuracy of the synchronization depends on several parameters:
• The nominal clock frequency (F
13 dominant bits (at 0)
Break Field
Initial CD
Initial FP
Initial CD
Initial FP
Start
bit
2 Tbit
1 recessive bit
Delimiter
Break
(at 1)
Reset
Start
Bit
Nom
2 Tbit
1
) (the theoretical slave node clock frequency)
0
8 Tbit
Synch Byte = 0x55
1
Synch Field
0
2 Tbit
1
0
1
0
000_0011_0001_0110_1101
2 Tbit
Stop
Bit
0000_0110_0010_1101
101
Start
Bit
ID0 ID1 ID2 ID3 ID4 ID5 ID6 ID7
Stop
bit
11057B–ATARM–28-May-12
11057B–ATARM–28-May-12
Stop
Bit
Section