ATSAM3X4EA-AU Atmel, ATSAM3X4EA-AU Datasheet - Page 540

• Manufacturer Part Number: ATSAM3X4EA-AU
• Description: ARM Microcontrollers - MCU QFP144,GREEN, IND TEMP, MRL A
• Manufacturer: Atmel

Specifications of ATSAM3X4EA-AU

• Rohs: yes
• Core: ARM Cortex M3
• Processor Series: SAM3X
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 84 MHz
• Program Memory Size: 256 KB
• Data Ram Size: 64 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 2.4 V to 3.6 V
• Operating Temperature Range: - 40 C to +85 C
• Package / Case: LQFP-144
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 60

29.1.5.4
29.1.6
540
540
SAM3X/A
SAM3X/A
Divider and PLL Block
Main Clock Frequency Counter
The selection is made by writing the MOSCSEL bit in the Main Oscillator Register
(CKGR_MOR). The switch of the Main Clock source is glitch free, so there is no need to run out
of SLCK, PLLACKor UPLLCK in order to change the selection. The MOSCSELS bit of the
Power Management Controller Status Register (PMC_SR) allows knowing when the switch
sequence is done.
Setting the MOSCSELS bit in PMC_IMR can trigger an interrupt to the processor.
The device features a Main Clock frequency counter that provides the frequency of the Main
Clock.
The Main Clock frequency counter is reset and starts incrementing at the Main Clock speed after
the next rising edge of the Slow Clock in the following cases:
Then, at the 16th falling edge of Slow Clock, the MAINFRDY bit in the Clock Generator Main
Clock Frequency Register (CKGR_MCFR) is set and the counter stops counting. Its value can
be read in the MAINF field of CKGR_MCFR and gives the number of Main Clock cycles during
16 periods of Slow Clock, so that the frequency of the 4/8/12 MHz Fast RC oscillator or 3 to 20
MHz Crystal or Ceramic Resonator-based oscillator can be determined.
The device features one Divider/PLL Block that permits a wide range of frequencies to be
selected on either the master clock, the processor clock or the programmable clock outputs.
Additionally, they provide a 48 MHz signal to the embedded USB device port regardless of the
frequency of the main clock.
Figure 29-4
Figure 29-4. Dividers and PLL Block Diagram
• when the 4/8/12 MHz Fast RC oscillator clock is selected as the source of Main Clock and
• when the 3 to 20 MHz Crystal or Ceramic Resonator-based oscillator is selected as the
• when the Main Clock Oscillator selection is modified
when this oscillator becomes stable (i.e., when the MOSCRCS bit is set)
source of Main Clock and when this oscillator becomes stable (i.e., when the MOSCXTS bit
is set)
shows the block diagram of the dividers and PLL blocks.
MAINCK
SLCK
Divider
DIVA
PLLACOUNT
Counter
PLLA
MULA
PLLA
OUTA
LOCKA
PLLACK
11057B–ATARM–28-May-12
11057B–ATARM–28-May-12