ATSAM3X4EA-AU Atmel, ATSAM3X4EA-AU Datasheet - Page 82

• Manufacturer Part Number: ATSAM3X4EA-AU
• Description: ARM Microcontrollers - MCU QFP144,GREEN, IND TEMP, MRL A
• Manufacturer: Atmel

Specifications of ATSAM3X4EA-AU

• Rohs: yes
• Core: ARM Cortex M3
• Processor Series: SAM3X
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 84 MHz
• Program Memory Size: 256 KB
• Data Ram Size: 64 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 2.4 V to 3.6 V
• Operating Temperature Range: - 40 C to +85 C
• Package / Case: LQFP-144
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 60

Table 12-9.
1.
2.
3.
4.
5.
6.
12.6.3
12.6.3.1
12.6.3.2
82
82
Exception
number
4
5
6
7-10
11
12-13
14
15
16 and above
To simplify the software layer, the CMSIS only uses IRQ numbers and therefore uses negative values for exceptions other than
See
See
See the “Peripheral Identifiers” section of the datasheet.
See
Increasing in steps of 4.
(1)
SAM3X/A
SAM3X/A
Exception handlers
interrupts. The IPSR returns the Exception number, see
“Vector table” on page 83
“System Handler Priority Registers” on page
“Interrupt Priority Registers” on page
Interrupt Service Routines (ISRs)
Fault handlers
Properties of the different exception types (Continued)
IRQ
number
1)
-12
-11
-10
-
-5
-
-2
-1
0 and
above
(4)
(
For an asynchronous exception, other than reset, the processor can execute another instruction
between when the exception is triggered and when the processor enters the exception handler.
Privileged software can disable the exceptions that
figurable priority, see:
For more information about hard faults, memory management faults, bus faults, and usage
faults, see
The processor handles exceptions using:
Interrupts IRQ0 to IRQ29 are the exceptions handled by ISRs.
Hard fault, memory management fault, usage fault, bus fault are fault exceptions handled by the
fault handlers.
Exception
type
Memory
management fault
Bus fault
Usage fault
-
SVCall
-
PendSV
SysTick
Interrupt (IRQ)
•
•
“System Handler Control and State Register” on page 183
“Interrupt Clear-enable Registers” on page
for more information.
“Fault handling” on page
164.
Priority
Configurable
Configurable
Configurable
-
Configurable
-
Configurable
Configurable
Configurable
180.
“Interrupt Program Status Register” on page
87.
(3)
(3)
(3)
(3)
(3)
(3)
(5)
Vector address
or offset
0x00000010
0x00000014
0x00000018
Reserved
0x0000002C
Reserved
0x00000038
0x0000003C
0x00000040 and
above
160.
(6)
Table 12-9 on page 81
(2)
Activation
Synchronous
Synchronous when precise,
asynchronous when imprecise
Synchronous
-
Synchronous
-
Asynchronous
Asynchronous
Asynchronous
shows as having con-
11057B–ATARM–28-May-12
11057B–ATARM–28-May-12
65.