LPC1317FHN33,551 NXP Semiconductors, LPC1317FHN33,551 Datasheet - Page 2

• Manufacturer Part Number: LPC1317FHN33,551
• Description: ARM Microcontrollers - MCU 32bit ARM Cortex-M3 64KB Flash 10KB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1317FHN33,551

• Rohs: yes
• Core: ARM Cortex M3
• Processor Series: LPC1317
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 72 MHz
• Program Memory Size: 64 KB
• Data Ram Size: 8 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 2 V to 3.6 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
LPC1315_16_17_45_46_47
Product data sheet
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Debug options:
Digital peripherals:
Analog peripherals:
Serial interfaces:
Clock generation:
Power control:
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Standard JTAG test interface for BSDL.
Serial Wire Debug.
Support for ETM ARM Cortex-M3 debug time stamping.
Up to 51 General Purpose I/O (GPIO) pins with configurable pull-up/pull-down
resistors, repeater mode, input inverter, and pseudo open-drain mode. Eight pins
support programmable glitch filter.
Up to 8 GPIO pins can be selected as edge and level sensitive interrupt sources.
Two GPIO grouped interrupt modules enable an interrupt based on a
programmable pattern of input states of a group of GPIO pins.
High-current source output driver (20 mA) on one pin (P0_7).
High-current sink driver (20 mA) on true open-drain pins (P0_4 and P0_5).
Four general purpose counter/timers with a total of up to 8 capture inputs and 13
match outputs.
Programmable Windowed WatchDog Timer (WWDT) with a internal low-power
WatchDog Oscillator (WDO).
Repetitive Interrupt Timer (RI Timer).
12-bit ADC with eight input channels and sampling rates of up to 500 kSamples/s.
USB 2.0 full-speed device controller (LPC1345/46/47) with on-chip ROM-based
USB driver library.
USART with fractional baud rate generation, internal FIFO, a full modem control
handshake interface, and support for RS-485/9-bit mode and synchronous mode.
USART supports an asynchronous smart card interface (ISO 7816-3).
Two SSP controllers with FIFO and multi-protocol capabilities.
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a data rate of up to 1 Mbit/s with multiple address recognition and monitor mode.
Crystal Oscillator with an operating range of 1 MHz to 25 MHz (system oscillator)
with failure detector.
12 MHz high-frequency Internal RC oscillator (IRC) trimmed to 1 % accuracy over
the entire voltage and temperature range. The IRC can optionally be used as a
system clock.
Internal low-power, low-frequency WatchDog Oscillator (WDO) with programmable
frequency output.
PLL allows CPU operation up to the maximum CPU rate with the system oscillator
or the IRC as clock sources.
A second, dedicated PLL is provided for USB (LPC1345/46/47).
Clock output function with divider that can reflect the crystal oscillator, the main
clock, the IRC, or the watchdog oscillator.
Four reduced power modes: Sleep, Deep-sleep, Power-down, and Deep
power-down.
Power profiles residing in boot ROM allow optimized performance and minimized
power consumption for any given application through one simple function call.
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C-bus interface supporting the full I
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 20 September 2012
LPC1315/16/17/45/46/47
2
C-bus specification and Fast-mode Plus with
32-bit ARM Cortex-M3 microcontroller
© NXP B.V. 2012. All rights reserved.
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