LPC1317FHN33,551 NXP Semiconductors, LPC1317FHN33,551 Datasheet - Page 55

• Manufacturer Part Number: LPC1317FHN33,551
• Description: ARM Microcontrollers - MCU 32bit ARM Cortex-M3 64KB Flash 10KB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1317FHN33,551

• Rohs: yes
• Core: ARM Cortex M3
• Processor Series: LPC1317
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 72 MHz
• Program Memory Size: 64 KB
• Data Ram Size: 8 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 2 V to 3.6 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
[8]
[9]
[10] A Fast-mode I
LPC1315_16_17_45_46_47
Product data sheet
Fig 24. I
The maximum t
t
SCL signal. If the clock stretches the SCL, the data must be valid by the set-up time before it releases the clock.
tSU;DAT is the data set-up time that is measured with respect to the rising edge of SCL; applies to data in transmission and the
acknowledge.
This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the
LOW period of the SCL signal, it must output the next data bit to the SDA line t
Standard-mode I
VD;ACK
SDA
SCL
2
by a transition time (see UM10204). This maximum must only be met if the device does not stretch the LOW period (t
C-bus pins clock timing
70 %
30 %
S
2
t
C-bus device can be used in a Standard-mode I
f
HD;DAT
2
C-bus specification) before the SCL line is released. Also the acknowledge timing must meet this set-up time.
t
f
could be 3.45 s and 0.9 s for Standard-mode and Fast-mode but must be less than the maximum of t
70 %
30 %
1 / f
SCL
t
HD;DAT
70 %
30 %
70 %
30 %
All information provided in this document is subject to legal disclaimers.
t
SU;DAT
Rev. 3 — 20 September 2012
70 %
30 %
2
C-bus system but the requirement t
t
LOW
LPC1315/16/17/45/46/47
r(max)
t
HIGH
+ t
32-bit ARM Cortex-M3 microcontroller
70 %
30 %
SU;DAT
t
VD;DAT
= 1000 + 250 = 1250 ns (according to the
SU;DAT
= 250 ns must then be met.
© NXP B.V. 2012. All rights reserved.
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LOW
VD;DAT
55 of 77
) of the
or