LPC1317FHN33,551 NXP Semiconductors, LPC1317FHN33,551 Datasheet - Page 36

• Manufacturer Part Number: LPC1317FHN33,551
• Description: ARM Microcontrollers - MCU 32bit ARM Cortex-M3 64KB Flash 10KB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1317FHN33,551

• Rohs: yes
• Core: ARM Cortex M3
• Processor Series: LPC1317
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 72 MHz
• Program Memory Size: 64 KB
• Data Ram Size: 8 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 2 V to 3.6 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
LPC1315_16_17_45_46_47
Product data sheet
CAUTION
7.18.6.3 Code security (Code Read Protection - CRP)
7.18.6.4 APB interface
7.18.6.5 AHBLite
7.18.6.6 External interrupt inputs
7.19 Emulation and debugging
This feature of the LPC1315/16/17/45/46/47 allows user to enable different levels of
security in the system so that access to the on-chip flash and use of the Serial Wire
Debugger (SWD) and In-System Programming (ISP) can be restricted. When needed,
CRP is invoked by programming a specific pattern into a dedicated flash location. IAP
commands are not affected by the CRP.
In addition, ISP entry via the PIO0_1 pin can be disabled without enabling CRP. For
details see the LPC1315/16/17/45/46/47 user manual.
There are three levels of Code Read Protection:
In addition to the three CRP levels, sampling of pin PIO0_1 for valid user code can be
disabled. For details see the LPC1315/16/17/45/46/47 user manual.
The APB peripherals are located on one APB bus.
The AHBLite connects the CPU bus of the ARM Cortex-M3 to the flash memory, the main
static RAM, and the ROM.
All GPIO pins can be level or edge sensitive interrupt inputs.
Debug functions are integrated into the ARM Cortex-M3. Serial wire debug functions are
supported in addition to a standard JTAG boundary scan. The ARM Cortex-M0 is
configured to support up to four breakpoints and two watch points.
1. CRP1 disables access to the chip via the SWD and allows partial flash update
2. CRP2 disables access to the chip via the SWD and only allows full flash erase and
3. Running an application with level CRP3 selected fully disables any access to the chip
(excluding flash sector 0) using a limited set of the ISP commands. This mode is
useful when CRP is required and flash field updates are needed but all sectors can
not be erased.
update using a reduced set of the ISP commands.
via the SWD pins and the ISP. This mode effectively disables ISP override using
PIO0_1 pin, too. It is up to the user’s application to provide (if needed) flash update
mechanism using IAP calls or call reinvoke ISP command to enable flash update via
the USART.
If level three Code Read Protection (CRP3) is selected, no future factory testing can be
performed on the device.
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 20 September 2012
LPC1315/16/17/45/46/47
32-bit ARM Cortex-M3 microcontroller
© NXP B.V. 2012. All rights reserved.
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