LPC1317FHN33,551 NXP Semiconductors, LPC1317FHN33,551 Datasheet - Page 24

• Manufacturer Part Number: LPC1317FHN33,551
• Description: ARM Microcontrollers - MCU 32bit ARM Cortex-M3 64KB Flash 10KB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1317FHN33,551

• Rohs: yes
• Core: ARM Cortex M3
• Processor Series: LPC1317
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 72 MHz
• Program Memory Size: 64 KB
• Data Ram Size: 8 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 2 V to 3.6 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
7. Functional description
LPC1315_16_17_45_46_47
Product data sheet
7.1 On-chip flash programming memory
7.2 EEPROM
7.3 SRAM
7.4 On-chip ROM
7.5 Memory map
The LPC1315/16/17/45/46/47 contain up to 64 kB on-chip flash program memory. The
flash can be programmed using In-System Programming (ISP) or In-Application
Programming (IAP) via the on-chip boot loader software. Flash updates via USB are
supported as well.
The flash memory is divided into 4 kB sectors with each sector consisting of 16 pages.
Individual pages of 256 byte each can be erased using the IAP erase page command.
The LPC1315/16/17/45/46/47 contain 2 kB or 4 kB of on-chip byte-erasable and
byte-programmable EEPROM data memory. The EEPROM can be programmed using
In-Application Programming (IAP) via the on-chip boot loader software.
The LPC1315/16/17/45/46/47 contain a total of 8 kB, 10 kB, or 12 kB on-chip static RAM
memory.
The on-chip ROM contains the boot loader and the following Application Programming
Interfaces (APIs):
The LPC1315/16/17/45/46/47 incorporates several distinct memory regions, shown in the
following figures.
user program viewpoint following reset. The interrupt vector area supports address
remapping.
The AHB peripheral area is 2 MB in size and is divided to allow for up to 128 peripherals.
The APB peripheral area is 512 kB in size and is divided to allow for up to 32 peripherals.
Each peripheral of either type is allocated 16 kB of space. This allows simplifying the
address decoding for each peripheral.
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•
•
•
•
In-System Programming (ISP) and In-Application Programming (IAP) support for flash
including IAP erase page command.
IAP support for EEPROM
USB API (HID, CDC, and MSC drivers) (LPC1345/46/47 only)
Power profiles for configuring power consumption and PLL settings
Flash updates via USB supported (LPC1345/46/47 only)
All information provided in this document is subject to legal disclaimers.
Figure 8
Rev. 3 — 20 September 2012
shows the overall map of the entire address space from the
LPC1315/16/17/45/46/47
32-bit ARM Cortex-M3 microcontroller
© NXP B.V. 2012. All rights reserved.
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