LPC1111FHN33/102'5 NXP Semiconductors, LPC1111FHN33/102'5 Datasheet - Page 354

• Manufacturer Part Number: LPC1111FHN33/102'5
• Description: ARM Microcontrollers - MCU CORTEX-M0 8 KB FL 4 KB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1111FHN33/102'5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1111
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Mounting Style: SMD/SMT
• Interface Type: I2C, SPI, UART
• Number Of Programmable I/os: 42
• Number Of Timers: 4
• Program Memory Type: Flash
• Factory Pack Quantity: 4000

20.1 How to read this chapter
20.2 Basic configuration
20.3 Features
20.4 Applications
UM10398
User manual
The 32-bit timer blocks are identical for all LPC111x, LPC11D14, and LPC11Cxx parts.
The CT32B0/1 are configured using the following registers:
1. Pins: The CT32B0/1 pins must be configured in the IOCONFIG register block
2. Power and peripheral clock: In the SYSAHBCLKCTRL register, set bit 9 and bit 10
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UM10398
Chapter 20: LPC1100/LPC1100C/LPC1100L series: 32-bit
counter/timer CT32B0/1
Rev. 12 — 24 September 2012
(Section
(Table
Table
Two 32-bit counter/timers with a programmable 32-bit prescaler.
Counter or Timer operation.
One 32-bit capture channel that can take a snapshot of the timer value when an input
signal transitions. A capture event may also optionally generate an interrupt.
Four 32-bit match registers that allow:
– Continuous operation with optional interrupt generation on match.
– Stop timer on match with optional interrupt generation.
– Reset timer on match with optional interrupt generation.
Four external outputs corresponding to match registers with the following capabilities:
– Set LOW on match.
– Set HIGH on match.
– Toggle on match.
– Do nothing on match.
For each timer, up to four match registers can be configured as PWM allowing to use
up to three match outputs as single edge controlled PWM outputs.
Interval timer for counting internal events
Pulse Width Demodulator via capture input
Free running timer
Pulse Width Modulator via match outputs
20).
21). The peripheral clock (PCLK) is provided by the system clock (see
7.4).
All information provided in this document is subject to legal disclaimers.
Rev. 12 — 24 September 2012
© NXP B.V. 2012. All rights reserved.
User manual
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