LPC1111FHN33/102'5 NXP Semiconductors, LPC1111FHN33/102'5 Datasheet - Page 443
LPC1111FHN33/102'5
Manufacturer Part Number
LPC1111FHN33/102'5
Description
ARM Microcontrollers - MCU CORTEX-M0 8 KB FL 4 KB SRAM
Manufacturer
NXP Semiconductors
Datasheet
1.LPC1113FHN333035.pdf
(538 pages)
Specifications of LPC1111FHN33/102'5
Rohs
yes
Core
ARM Cortex M0
Processor Series
LPC1111
Data Bus Width
32 bit
Maximum Clock Frequency
50 MHz
On-chip Adc
Yes
Operating Supply Voltage
1.8 V to 3.6 V
Operating Temperature Range
- 65 C to + 150 C
Mounting Style
SMD/SMT
Interface Type
I2C, SPI, UART
Number Of Programmable I/os
42
Number Of Timers
4
Program Memory Type
Flash
Factory Pack Quantity
4000
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27.6 Debug notes
UM10398
User manual
27.6.1 Debug limitations
27.6.2 Debug connections
Important: The user should be aware of certain limitations during debugging. The most
important is that, due to limitations of the ARM Cortex-M0 integration, the
LPC111x/LPC11Cxx cannot wake up in the usual manner from Deep-sleep mode. It is
recommended not to use this mode during debug.
Another issue is that debug mode changes the way in which reduced power modes work
internal to the ARM Cortex-M0 CPU, and this ripples through the entire system. These
differences mean that power measurements should not be made while debugging, the
results will be higher than during normal operation in an application.
During a debugging session, the System Tick Timer is automatically stopped whenever
the CPU is stopped. Other peripherals are not affected.
For debugging purposes, it is useful to provide access to the ISP entry pin PIO0_1. This
pin can be used to recover the part from configurations which would disable the SWD port
such as improper PLL configuration, reconfiguration of SWD pins as ADC inputs, entry
into Deep power-down mode out of reset, etc. This pin can be used for other functions
such as GPIO, but it should not be held low on power-up or reset.
Fig 93. Connecting the SWD pins to a standard SWD connector
The VTREF pin on the SWD connector enables the debug connector to match the target voltage.
SWDIO
SWCLK
nSRST
VTREF
All information provided in this document is subject to legal disclaimers.
GND
Rev. 12 — 24 September 2012
Gnd
Chapter 27: LPC111x/LPC11Cxx Serial Wire Debug (SWD)
VDD
ISP entry
SWDIO
SWCLK
RESET
PIO0_1
UM10398
© NXP B.V. 2012. All rights reserved.
LPC111x
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