LPC1111FHN33/102'5 NXP Semiconductors, LPC1111FHN33/102'5 Datasheet - Page 368

• Manufacturer Part Number: LPC1111FHN33/102'5
• Description: ARM Microcontrollers - MCU CORTEX-M0 8 KB FL 4 KB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1111FHN33/102'5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1111
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Mounting Style: SMD/SMT
• Interface Type: I2C, SPI, UART
• Number Of Programmable I/os: 42
• Number Of Timers: 4
• Program Memory Type: Flash
• Factory Pack Quantity: 4000

21.1 How to read this chapter
21.2 Basic configuration
21.3 Features
UM10398
User manual
The 32-bit timer blocks are identical for all LPC1100XL parts.
Compared to the timer block for the LPC1100/LPC1100L/LPC1100C series, the following
features have been added:
The CT32B0/1 are configured using the following registers:
1. Pins: The CT32B0/1 pins must be configured in the IOCONFIG register block
2. Power and peripheral clock: In the SYSAHBCLKCTRL register, set bit 9 and bit 10
•
•
•
•
•
•
•
•
•
UM10398
Chapter 21: LPC1100XL series: 32-bit counter/timer CT32B0/1
Rev. 12 — 24 September 2012
One additional capture input for each timer.
Capture-clear function for easy pulse-width measurement (see
(Section
(Table
Table
Two 32-bit counter/timers with a programmable 32-bit prescaler.
Counter or Timer operation.
The timer and prescaler may be configured to be cleared on a designated capture
event. This feature permits easy pulse-width measurement by clearing the timer on
the leading edge of an input pulse and capturing the timer value on the trailing edge.
Two 32-bit capture channels that can take a snapshot of the timer value when an input
signal transitions. A capture event may also optionally generate an interrupt.
Four 32-bit match registers that allow:
– Continuous operation with optional interrupt generation on match.
– Stop timer on match with optional interrupt generation.
– Reset timer on match with optional interrupt generation.
Up to four external outputs corresponding to match registers with the following
capabilities:
– Set LOW on match.
– Set HIGH on match.
– Toggle on match.
– Do nothing on match.
For each timer, up to four match registers can be configured as PWM allowing to use
up to three match outputs as single edge controlled PWM outputs.
20).
21). The peripheral clock (PCLK) is provided by the system clock (see
7.4).
All information provided in this document is subject to legal disclaimers.
Rev. 12 — 24 September 2012
Section
© NXP B.V. 2012. All rights reserved.
User manual
21.7.11).
368 of 538