PCI-MT32-XP-N1 Lattice, PCI-MT32-XP-N1 Datasheet - Page 104

• Manufacturer Part Number: PCI-MT32-XP-N1
• Description: FPGA - Field Programmable Gate Array PCI Master/Target 32B
• Manufacturer: Lattice

Specifications of PCI-MT32-XP-N1

• Factory Pack Quantity: 1

Lattice Semiconductor
Table 2-40. 32-bit Target Burst Write Transaction with a 32-bit Local Interface
IPUG18_09.2, November 2010
CLK
1
2
3
4
5
6
7
8
9
Turn around
PCI Data
Address
Phase
Data 1
Data 2
Data 3
Wait
Wait
Wait
Idle
The PCI master asserts framen and drives ad[31:0] and cben[3:0].
The PCI master drives the first byte enables (Byte Enable 1) on cben[3:0]. If the master is ready
to write data, it asserts irdyn and drives the first DWORD (Data 1) on ad[31:0]. The PCI IP core
starts to decode the address and command and drives the lt_address_out to the back-end.
If there is an address match, the Core drives the bar_hit signals on the Local Interface. The back-
end can use the bar_hit as a chip select.
If the DEVSEL_TIMING is set to slow, the Core asserts devseln on clock after bar_hit. If the
back-end will be ready to write data in two cycles, it can assert lt_rdyn.
trdyn is asserted since lt_rdyn was asserted the previous cycle.
If the back-end keeps lt_rdyn asserted for the previous cycle, the Core keeps trdyn asserted
and puts Data 1 on l_data_out. If both irdyn and trdyn are asserted on the previous cycle, the
master drives the next byte enables (Byte Enable 2) on cben[3:0]. If the master is still ready to
write data, it keeps irdyn asserted and drives the next DWORD (Data 2) on ad[31:0]. If both
irdyn and lt_rdyn are asserted on the previous cycle, the Core asserts lt_data_xfern to the
back-end to signify Data 1 was transferred successfully. With lt_data_xfern asserted, the back-
end can safely write Data 1 and increment the address counter.
If the back-end keeps lt_rdyn asserted for the previous cycle, the Core keeps trdyn asserted
and puts Data 2 on l_data_out.
If both irdyn and trdyn are asserted on the previous cycle, the master drives the next byte
enables (Byte Enable 3) on cben[3:0]. If the master is still ready to write data, it keeps irdyn
asserted and drives the next DWORD (Data 3) on ad[31:0].
The master signals the end of the burst when it de-asserts framen. If both irdyn and lt_rdyn
are asserted on the previous cycle, the Core keeps lt_data_xfern asserted to the back-end to
signify Data 2 was transferred successfully.
If the back-end keeps lt_rdyn asserted for the previous cycle, the Core puts Data 3 on
l_data_out.
If both irdyn and trdyn are asserted on the previous cycle, the master relinquishes control of
framen, ad and cben. It also de-asserts irdyn if both trdyn and irdyn were asserted last
cycle.
If both irdyn and lt_rdyn are asserted on the previous cycle, the Core keeps lt_data_xfern
asserted to the back-end to signify Data 3 was transferred successfully. With lt_data_xfern
asserted the back-end can safely write Data 3 and increment the address counter.
The PCI IP core de-asserts both devseln and trdyn if both trdyn and irdyn were asserted last
cycle.
The target signals to the back-end that the transaction is complete by clearing bar_hit. It also de-
asserts lt_data_xfern. The Core relinquishes control of devseln and trdyn.
104
Description
Functional Description
PCI IP Core User’s Guide