PCI-MT32-XP-N1 Lattice, PCI-MT32-XP-N1 Datasheet - Page 40

• Manufacturer Part Number: PCI-MT32-XP-N1
• Description: FPGA - Field Programmable Gate Array PCI Master/Target 32B
• Manufacturer: Lattice

Specifications of PCI-MT32-XP-N1

• Factory Pack Quantity: 1

Lattice Semiconductor
Functional Description
32-bit PCI Master with a 64-Bit Local Bus
This section discusses read and write transactions executed by the PCI IP core configured with a 32-bit PCI bus
and a 64-bit local bus. The 32-bit PCI master transactions, described in the 32-Bit PCI Master and 32-Bit Local Bus
section, are similar to these master transactions; however; the data is handled differently at the Local Master Inter-
face. Two 32-bit PCI data phases are required to transfer 64 bits of data to the Local Master Interface.
The Local Master Interface control latches the complete QWORD and routes the proper DWORD to the PCI data
bus. The lm_ldata_xfern and lm_hdata_xfern signals specify which DWORD is transferred.
If the starting address is aligned with QWORD, the first DWORD is assumed to be the lower DWORD of a QWORD
and is placed on the PCI data bus. Otherwise, the upper DWORD is placed on the PCI data bus.
The 64-bit memory read transaction is similar to the 32-bit target read transaction with additional PCI signals
required for 64-bit signaling.
Figure 2-11
and
Table 2-15
illustrate a basic 64-bit read transaction.
IPUG18_09.2, November 2010
40
PCI IP Core User’s Guide