PCI-MT32-XP-N1 Lattice, PCI-MT32-XP-N1 Datasheet - Page 144

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PCI-MT32-XP-N1

Manufacturer Part Number
PCI-MT32-XP-N1
Description
FPGA - Field Programmable Gate Array PCI Master/Target 32B
Manufacturer
Lattice
Datasheet

Specifications of PCI-MT32-XP-N1

Factory Pack Quantity
1
Lattice Semiconductor
IP Core Generation
Figure 4-1. IPexpress Dialog Box (Diamond Version)
Note that if the IPexpress tool is called from within an existing project, Project Path, Module Output (Design Entry in
ispLEVER), Device Family and Part Name default to the specified project parameters. Refer to the IPexpress tool
online help for further information.
To create a custom configuration, the user clicks the Customize button in the IPexpress tool dialog box to display
the PCI IP core Configuration GUI, as shown in
Figure
4-2. From this dialog box, the user can select the IP param-
eter options specific to their application. Refer to
“Parameter Settings” on page 136
for more information on the PCI
IP core parameter settings.
IPUG18_09.2, November 2010
144
PCI IP Core User’s Guide

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