PCI-MT32-XP-N1 Lattice, PCI-MT32-XP-N1 Datasheet - Page 97

• Manufacturer Part Number: PCI-MT32-XP-N1
• Description: FPGA - Field Programmable Gate Array PCI Master/Target 32B
• Manufacturer: Lattice

Specifications of PCI-MT32-XP-N1

• Factory Pack Quantity: 1

Lattice Semiconductor
Functional Description
In legacy systems, I/O space is limited. The system generally uses I/O space for vital system components such as
interrupt controllers. These system components are spread throughout the I/O space, leaving only small gaps for
additional devices that require I/O space. If I/O space is used in a legacy system, it is limited to 256 bytes.
By definition, read and write transactions to I/O space can only be completed using 32-bit PCI transactions. Decod-
ing all 32 bits in the address and determining which byte enables (cben[3:0]) are supported is necessary. The
back-end application responds with a target abort if any unsupported byte enable combinations are requested.
Advanced Target Transactions
Some PCI applications require more than basic read and write transactions. For these applications, the PCI Local
Bus Specification, Revision 3.0 offers advanced features to handle the more difficult aspects of the PCI bus. The
advanced features are used to provide the PCI application with more flexibility and improve the overall PCI system
performance. The following sections offer more detail on these advanced PCI bus features.
Wait States
Care must be taken when processing wait states to be compliant with the PCI Local Bus Specification, Revision
3.0. Once a PCI master or a PCI target signals that it is ready to send or receive data, it must complete the current
PCI data phase. For example, if the PCI IP core is ready to write data and the PCI master inserts wait states, the
PCI IP core must wait to write the data until the master is ready again. Additionally, if the PCI IP core has commit-
ted to a data phase by asserting trdyn, it can not insert any wait states until the next data phase. Coincident mas-
ter and target wait state insertion is also a possibility. Refer to the PCI Specification for more information regarding
coincident wait state insertion.
Two types of wait states that can occur on the PCI bus. The first is master wait state insertion. When the PCI mas-
ter inserts wait states, the PCI IP core must hold off data until the PCI master is ready. The PCI IP core inserts the
second type of wait states. The back-end application controls the PCI IP core’s wait state insertion via the Local
Target Interface.
Figure 2-32
and
Table 2-37
illustrate master-inserted and target-inserted wait states for read transactions. The fig-
ure illustrates how the PCI interface correlates to the Local Target Interface. The table gives a clock-by-clock
description of each event in the figure.
IPUG18_09.2, November 2010
97
PCI IP Core User’s Guide