PCI-MT32-XP-N1 Lattice, PCI-MT32-XP-N1 Datasheet - Page 19

• Manufacturer Part Number: PCI-MT32-XP-N1
• Description: FPGA - Field Programmable Gate Array PCI Master/Target 32B
• Manufacturer: Lattice

Specifications of PCI-MT32-XP-N1

• Factory Pack Quantity: 1

Lattice Semiconductor
IPUG18_09.2, November 2010
Figure 2-2. PCI IP Core Configuration Space
Vendor ID: The Vendor ID is a 16-bit, read-only field used to identify the manufacturer of the product. The Vendor
ID is set using the VENDOR_ID parameter. The Vendor ID is assigned by the PCI SIG to ensure uniqueness. Con-
tact PCI SIG (www.pcisig.org) to obtain a unique Vendor ID.
Device ID: The Device ID is a 16-bit, read-only field that is defined by the manufacturer used to uniquely identify a
particular product or model. The Device ID is set using the DEVICE_ID parameter. Its default value is 0000h.
Revision ID: The Revision ID is an 8-bit, read-only device-specific field that is set using the REVISION_ID param-
eter. This field is used by the manufacturer and should be viewed as an extension of the Device ID to distinguish
between different functional versions of a PCI product.
Class Code: The Class Code is a 24-bit, read-only register and is used to identify the generic functionality of a
device. The value of this register is determined by the CLASS_CODE parameter. The Class Code is broken up into
three bytes. The upper byte holds the base class code; the middle byte holds the sub-class code. In addition, the
lower byte holds the programming interface. The Class Code information is located in the PCI Local Bus Specifica-
tion, Revision 3.0. The default setting for this register is FF0000h.
Command Register: The Command Register is a 16-bit read/write register that provides coarse control over the
device. It is located at the lower 16 bits of address 04h in the Configuration Space. Using this register, the memory
and I/O space can be disabled to allow only configuration accesses. This register also controls the parity error
response and the serrn signal.
the PCI IP core.
Note: Shaded sections indicate reserved and
unused sections in the configuration space. All
unused and reserved registers return 0s.
MAX_LAT
Figure 2-3
BIST
Status Register
Subsystem ID
Device ID
Expansion ROM Base Address
Class Code
MIN_GNT
Reserved
and
Header
Cardbus CIS Pointer
Type
Base Address 0
Base Address 1
Base Address 2
Base Address 3
Base Address 4
Base Address 5
Table 2-5
Reserved
19
Subsystem Vendor ID
Interrupt
Latency
Command Register
Timer
Pin
illustrate the command register that is implemented in
Vendor ID
Line Size
Revision
Interrupt
Cap Ptr
Cache
Line
ID
0Ch
1Ch
2Ch
3Ch
00h
04h
08h
10h
14h
18h
20h
24h
28h
30h
34h
38h
Functional Description
PCI IP Core User’s Guide