PCI-MT32-XP-N1 Lattice, PCI-MT32-XP-N1 Datasheet - Page 105

• Manufacturer Part Number: PCI-MT32-XP-N1
• Description: FPGA - Field Programmable Gate Array PCI Master/Target 32B
• Manufacturer: Lattice

Specifications of PCI-MT32-XP-N1

• Factory Pack Quantity: 1

Lattice Semiconductor
Functional Description
64-Bit PCI Target with a 64-Bit Local Bus
The following discusses read and write burst transactions for the PCI IP core configured with a 64-bit PCI bus and
a 64-bit local bus.
Figure 2-36
and
Table 2-41
illustrate a 64-bit burst write transaction. The figure shows how the
PCI interface correlates to the local interface. The table gives a clock-by-clock description of each event that occurs
in the figure.
The 32-bit burst transaction, as described in the 32-Bit PCI Bus and a 32-Bit Local Bus section, is similar to a 32-bit
burst transaction for the 64-bit PCI IP core configuration. When the 64-bit target core responds to a 32-bit burst
transaction, the upper 32 bits of the data bus should be ignored.
IPUG18_09.2, November 2010
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PCI IP Core User’s Guide