PCI-MT32-XP-N1 Lattice, PCI-MT32-XP-N1 Datasheet - Page 98

• Manufacturer Part Number: PCI-MT32-XP-N1
• Description: FPGA - Field Programmable Gate Array PCI Master/Target 32B
• Manufacturer: Lattice

Specifications of PCI-MT32-XP-N1

• Factory Pack Quantity: 1

Lattice Semiconductor
IPUG18_09.2, November 2010
Figure 2-32. 32-bit Target Read Transaction with Master Wait State
Table 2-37. 32-bit Target Read Transaction with Master Wait State
CLK
1
2
3
4
5
6
7
lt_address_out
lt_data_xfern
l_ad_in[31:0]
bar_hit[5:0]
cben[3:0]
ad[31:0]
devseln
lt_r_nw
framen
lt_rdyn
irdyn
trdyn
Turn around The PCI master tri-states ad[31:0].The PCI master is ready to receive data. It asserts irdyn.
Master Wait
Target Wait The Core starts to decode the address and command.
Target Wait
Target Wait
par
clk
PCI Data
Address
Phase
Data 1
1
Don’t care
Command
Address
Bus
0x00
The PCI master asserts framen and drives ad[31:0] and cben[3:0].
If the DEVSEL_TIMING is set to slow, the Core asserts devseln one clock after bar_hit.
trdyn is kept asserted since the back-end logic did not assert lt_rdyn during clock cycle 3.
The back-end logic asserts lt_rdyn during this cycle.
The PCI IP core inserts a wait state as it has not yet asserted the trdyn signal. Since both irdyn
and lt_rdyn were asserted on the previous cycle, the Core asserts lt_data_xfern.
The Core asserts trdyn and drives Data 1 from the local target on to the PCI ad[31:0] bus. If
the PCI master is still ready to receive data, it keeps irdyn asserted and drives the next byte
enables (Byte Enables) on cben[3:0]. If the back-end kept lt_rdyn asserted in the previous
two cycles, the Core keeps trdyn asserted and puts Data 2 on ad[31:0].If both irdyn and
lt_rdyn are asserted on the previous cycle, the Core re-asserts lt_data_xfern to the back-
end.
The PCI master is not ready to receive data, it de-asserts irdyn If the back-end keeps lt_rdyn
asserted previous two cycles, the Core keeps trdyn asserted and puts Data 2 on ad[31:0].If
both irdyn and lt_rdyn are asserted on the previous cycle, the Core re-asserts
lt_data_xfern to the back-end. The back-end should increment the address counter.
2
Address
Parity
Don’t care
3
4
Don’t care
5
Don’t care
Data 1
Byte Enable 1
98
6
Data 1
Data 2
Description
Address
7
0x01
Data Parity
Data 3
1
8
Data 2
Data Parity 2
9
Data 3
Functional Description
Don’t care
10
PCI IP Core User’s Guide
Data Parity
3
11
0x00
12