PCI-MT32-XP-N1 Lattice, PCI-MT32-XP-N1 Datasheet - Page 85

• Manufacturer Part Number: PCI-MT32-XP-N1
• Description: FPGA - Field Programmable Gate Array PCI Master/Target 32B
• Manufacturer: Lattice

Specifications of PCI-MT32-XP-N1

• Factory Pack Quantity: 1

Lattice Semiconductor
IPUG18_09.2, November 2010
Figure 2-25
Table 2-30
Figure 2-25. 32-bit Target Single Write Transaction with a 32-bit Local Interface
lt_command_out[3:0]
l_data_out[31:0]
lt_cben_out[3:0]
lt_address_out
lt_data_xfern
bar_hit[5:0]
lt_accessn
gives a clock-by-clock description of the 32-bit write transaction.
cben[3:0]
ad[31:0]
devseln
illustrates an example of a basic 32-bit write transaction to the PCI IP core operating as a Target.
lt_r_nw
framen
lt_rdyn
trdyn
irdyn
par
clk
1
Don’t care
Don’t care
Command
Address
Bus
Don’t care
0x00
2
Address
Parity
3
Don’t care
Byte Enable 1
85
4
Data 1
Bus Command
Byte Enable 1
Data Parity 1
Address
5
0x01
6
Data 1
Functional Description
PCI IP Core User’s Guide
7
Don’t care
Don’t care
0x00
8