C8051F987-GMR Silicon Labs, C8051F987-GMR Datasheet - Page 114

• Manufacturer Part Number: C8051F987-GMR
• Description: 8-bit Microcontrollers - MCU 8kB 512B RAM
• Manufacturer: Silicon Labs

Specifications of C8051F987-GMR

• Rohs: yes
• Core: 8051
• Processor Series: C8051
• Data Bus Width: 8 bit

C8051F99x-C8051F98x
SFR Definition 8.13. CS0MD3: Capacitive Sense Mode 3
SFR Page = 0xF; SFR Address = 0xF3
114
Name
Reset
7:5
4:3
2:0
Bit
Type
Bit
CS0RP[1:0]
CS0LP[2:0]
Unused
Name
R/W
7
0
Read = 000b; Write = Don’t care
CS0 Ramp Selection.
These bits are used to compensate CS0 conversions for circuits requiring slower
ramp times. For most touch-sensitive switches, the default (fastest) value is suffi-
cient. See the discussion in Section 8.13 for more information.
00: Ramp time is less than 1.5 µs.
01: Ramp time is between 1.5 µs and 3 µs.
10: Ramp time is between 3 µs and 6 µs.
11: Ramp time is greater than 6 µs.
CS0 Low Pass Filter Selection.
These bits set the internal corner frequency of the CS0 low-pass filter. Higher val-
ues of CS0LP result in a lower internal corner frequency.
For most touch-sensitive switches, the default setting of 000b should be used. If
the CS0RP bits are adjusted from their default value, the CS0LP bits should nor-
mally be set to 001b. Settings higher than 001b will result in attenuated readings
from the CS0 module and should be used only under special circumstances. See
the discussion in Section 8.13 for more information.
R/W
6
0
R/W
5
0
R/W
Rev. 1.1
4
0
CS0RP[1:0]
Description
R/W
3
0
R/W
2
0
CS0LP[2:0]
R/W
1
0
R/W
0
0