C8051F987-GMR Silicon Labs, C8051F987-GMR Datasheet - Page 167
C8051F987-GMR
Manufacturer Part Number
C8051F987-GMR
Description
8-bit Microcontrollers - MCU 8kB 512B RAM
Manufacturer
Silicon Labs
Datasheet
1.C8051F986-GUR.pdf
(322 pages)
Specifications of C8051F987-GMR
Rohs
yes
Core
8051
Processor Series
C8051
Data Bus Width
8 bit
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SFR Definition 15.2. PMU0FL: Power Management Unit Flag
SFR Page = 0x0; SFR Address = 0xCE
Notes:
Name
Reset
Bit
7:1
Type
0
Bit
1. The Low Power Internal Oscillator cannot be disabled and the MCU cannot be placed in Suspend or Sleep
2. PMU0 requires two system clocks to update the wake-up source flags after waking from Suspend mode. The
Mode if any wake-up flags are set to 1. Software should clear all wake-up sources after each reset and after
each wake-up from Suspend or Sleep Modes.
wake-up source flags will read ‘0’ during the first two system clocks following the wake from Suspend mode.
CS0WK
Unused
Name
R
7
0
Unused
CS0 Wake-up Source
Enable and Flag
R
6
0
Description
R
5
0
Rev. 1.1
Don’t Care.
0: Disable wake-up on
CS0 event.
1: Enable wake-up on CS0
event.
R
4
0
C8051F99x-C8051F98x
Write
R
3
0
R
2
0
1,2
0000000
Set to 1 if CS0 event
caused the last wake-up.
R
1
0
Read
CS0WK
Varies
R/W
0
167
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