C8051F987-GMR Silicon Labs, C8051F987-GMR Datasheet - Page 301
C8051F987-GMR
Manufacturer Part Number
C8051F987-GMR
Description
8-bit Microcontrollers - MCU 8kB 512B RAM
Manufacturer
Silicon Labs
Datasheet
1.C8051F986-GUR.pdf
(322 pages)
Specifications of C8051F987-GMR
Rohs
yes
Core
8051
Processor Series
C8051
Data Bus Width
8 bit
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26.3. Capture/Compare Modules
Each module can be configured to operate independently in one of six operation modes: edge-triggered
capture, software timer, high-speed output, frequency output, 8 to 11-bit pulse width modulator, or 16-bit
pulse width modulator. Each module has Special Function Registers (SFRs) associated with it in the CIP-
51 system controller. These registers are used to exchange data with a module and configure the module's
mode of operation. Table 26.2 summarizes the bit settings in the PCA0CPMn and PCA0PWM registers
used to select the PCA capture/compare module’s operating mode. Note that all modules set to use 8, 9,
10, or 11-bit PWM mode must use the same cycle length (8–11 bits). Setting the ECCFn bit in a
PCA0CPMn register enables the module's CCFn interrupt.
Operational Mode
Capture triggered by positive edge on CEXn
Capture triggered by negative edge on CEXn
Capture triggered by any transition on CEXn
Software Timer
High Speed Output
Frequency Output
8-Bit Pulse Width Modulator (Note 7)
9-Bit Pulse Width Modulator (Note 7)
10-Bit Pulse Width Modulator (Note 7)
11-Bit Pulse Width Modulator (Note 7)
16-Bit Pulse Width Modulator
Notes:
Table 26.2. PCA0CPM and PCA0PWM Bit Settings for PCA Capture/Compare Modules
1. X = Don’t Care (no functional difference for individual module if 1 or 0).
2. A = Enable interrupts for this module (PCA interrupt triggered on CCFn set to 1).
3. B = Enable 8th, 9th, 10th or 11th bit overflow interrupt (Depends on setting of CLSEL[1:0]).
4. C = When set to 0, the digital comparator is off. For high speed and frequency output modes, the
5. D = Selects whether the Capture/Compare register (0) or the Auto-Reload register (1) for the associated
6. E = When set, a match event will cause the CCFn flag for the associated channel to be set.
7. All modules set to 8, 9, 10 or 11-bit PWM mode use the same cycle length setting.
associated pin will not toggle. In any of the PWM modes, this generates a 0% duty cycle (output = 0).
channel is accessed via addresses PCA0CPHn and PCA0CPLn.
Bit Number 7 6 5 4 3 2 1 0 7 6 5
Rev. 1.1
X X 1 0 0 0 0 A 0 X B XXX
X X 0 1 0 0 0 A 0 X B XXX
X X 1 1 0 0 0 A 0 X B XXX
X C 0 0 1 0 0 A 0 X B XXX
X C 0 0 1 1 0 A 0 X B XXX
X C 0 0 0 1 1 A 0 X B XXX
C8051F99x-C8051F98x
0 C 0 0 E 0 1 A 0 X B XXX
0 C 0 0 E 0 1 A D X B XXX
0 C 0 0 E 0 1 A D X B XXX
0 C 0 0 E 0 1 A D X B XXX
1 C 0 0 E 0 1 A 0 X B XXX
PCA0CPMn
PCA0PWM
4–2
1–0
XX
XX
XX
XX
XX
XX
XX
00
01
10
11
301
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