MCIMX508CZK8B Freescale Semiconductor, MCIMX508CZK8B Datasheet - Page 12

• Manufacturer Part Number: MCIMX508CZK8B
• Description: Processors - Application Specialized CODEX REV 1.1
• Manufacturer: Freescale Semiconductor
• Type: Multimedia Applicationsr

Specifications of MCIMX508CZK8B

• Core: ARM Cortex A8
• Processor Series: i.MX50

Modules List
12
BCH32/GPMI2 Raw NAND
System Fabric
Mnemonic
DRAM MC
and QoS
eCSPI-1
eCSPI-2
Block
CSPI
CCM
TPIU
EPIT
GPC
SRC
DAP
EIM
CTI
Clock Control
Module
Global Power
Controller
System Reset
Controller
Configurable
SPI, Enhanced
CSPI
Debug System
DRAM Memory
Controller
Static Memory
Controller
System with
ECC
System Fabric
and QoS
Enhanced
Periodic
Interrupt Timer
Block Name
i.MX50 Applications Processors for Consumer Products, Rev. 4
Table 4. i.MX50 Digital and Analog Modules (continued)
Clocks,
Resets, and
Power Control
Slave
Connectivity
Peripherals
System
Control
Peripherals
External
Memory
Interface
External
Memory
Interface
RawNAND
and SSP
Peripherals
System
Peripherals
Timer
Peripherals
Subsystem
These modules are responsible for clock and reset distribution in the system,
and also for system power management.
The system includes four PLLs.
Full-duplex enhanced synchronous serial interface, with data rate up to
66.5 Mbit/s (for eCSPI, master mode). It is configurable to support
Master/Slave modes, four chip selects to support multiple peripherals.
The Debug System provides real-time trace debug capability of both
instructions and data. It supports a trace protocol that is an integral part of the
ARM Real Time Debug solution (RealView).
Real-time tracing is controlled by specifying a set of triggering and filtering
resources, which include address and data comparators, three cross-system
triggers (CTI), counters, and sequencers.
Debug access port (DAP)—The DAP provides real-time access for the
debugger without halting the core to System memory and peripheral
registers. All debug configuration registers and Debugger access to JTAG
scan chains.
The DRAM MC consists of a DRAM memory controller and PHY, supporting
LPDDR2, DDR2, and LPDDR1 memories with clock frequencies up to
266 MHz with 32-bit interface. It is tightly linked with the system bus fabric and
employs advanced arbitration mechanism to maximize DRAM bandwidth
efficiency.
The EIM is an external static memory and generic host interface. It supports
up to a 32-bit interface (through pin-muxing) or a dedicated 16-bit muxed
interface. It can be used to interface to PSRAMs (sync and async), NOR-flash
or any external memory mapped peripheral.
The i.MX50 contains a fully hardware accelerated raw NAND flash solution
supporting SLC and MLC devices. The system consists of the GPMI2
module, which is driven by the APBH DMA engine to perform the NAND flash
interface function (supporting up to ONFI2.1). Coupled with the GPMI2 is the
BCH32 hardware error-correction engine which is an AXI bus-master and
supports up to 32-bits of correction over block sizes up to 1 Kbyte (that is,
supports up to 2 Kbyte code-size).
In order to aggregate the multitude of masters and memory mapped devices,
the i.MX50 contains a next-generation AMBA3 AXI bus fabric. In addition, the
i.MX50 contains a Quality of Service Controller IP (QoSC) which allows both
soft priority control and dynamic priority elevation. Software priority control
works for all masters but dynamic hardware control only works for EPDC and
eLCDIF.
Each EPIT is a 32-bit set and forget timer that starts counting after the EPIT
is enabled by software. It is capable of providing precise interrupts at regular
intervals with minimal processor intervention. It has a 12-bit prescaler for
division of input clock frequency to get the required time setting for the
interrupts to occur, and counter values can be programmed on the fly.
Brief Description
Freescale Semiconductor