MCIMX508CZK8B Freescale Semiconductor, MCIMX508CZK8B Datasheet - Page 68
MCIMX508CZK8B
Manufacturer Part Number
MCIMX508CZK8B
Description
Processors - Application Specialized CODEX REV 1.1
Manufacturer
Freescale Semiconductor
Type
Multimedia Applicationsr
Datasheet
1.MCIMX503EVM8B.pdf
(135 pages)
Specifications of MCIMX508CZK8B
Core
ARM Cortex A8
Processor Series
i.MX50
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Electrical Characteristics
4.8.1
The following diagrams and tables specify the timings related to the address and command pins, which
interfaces DDR2 and LPDDR1 memory devices.
68
DDR1
DDR2
DDR3
DDR4
DDR5
ID
DRAM Command & Address Output Timing—DDR2 and LPDDR1
DRAM_SDCLK_B
DRAM_SDCLK
DRAM_CS0
DRAM_RAS
DRAM_CAS
DRAM_SDWE
DRAM_ADDR
CK cycle time
CK high level width
CK low level width
Address and control output setup time
Address and control output hold time
Figure 28. DRAM Command/Address Output Timing—DDR2 and LPDDR1
i.MX50 Applications Processors for Consumer Products, Rev. 4
Description
DDR4
Table 44. EMI Command/Address AC Timing
DDR4
bank
row
DDR5
Symbol
DDR5
tCK
tCH
tCL
tIS
tIH
DDR4
DDR2
0.48 tCK
0.48 tCK
0.5 tCK
0.5 tCK
3.75
- 0.3
- 0.3
Min
column
DDR1
bank
0.52 tCK
0.52 tCK
Max
—
—
—
Freescale Semiconductor
DDR3
DDR5
Unit
ns
ns
ns
ns
ns
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