MCIMX508CZK8B Freescale Semiconductor, MCIMX508CZK8B Datasheet - Page 61

• Manufacturer Part Number: MCIMX508CZK8B
• Description: Processors - Application Specialized CODEX REV 1.1
• Manufacturer: Freescale Semiconductor
• Type: Multimedia Applicationsr

Specifications of MCIMX508CZK8B

• Core: ARM Cortex A8
• Processor Series: i.MX50

1
Freescale Semiconductor
WE10 Clock rise to EIM_OE valid
WE11 Clock rise to EIM_OE invalid 0.5t – 1.25 0.5t + 1.75 t – 1.25 t + 1.75 2t – 1.25 2t + 1.75 3t – 1.25 3t + 1.75
WE12 Clock rise to EIM_EBx valid 0.5t – 1.25 0.5t + 1.75 t – 1.25 t + 1.75 2t – 1.25 2t + 1.75 3t – 1.25 3t + 1.75
WE13 Clock rise to EIM_EBx
WE14 Clock rise to EIM_LBA valid 0.5t – 1.25 0.5t + 1.75 t – 1.25 t + 1.75 2t – 1.25 2t + 1.75 3t – 1.25 3t + 1.75
WE15 Clock rise to EIM_LBA
WE16 Clock rise to Output Data
WE17 Clock rise to Output Data
WE18 Input Data setup time to
WE19 Input Data hold time from
WE20 EIM_WAIT setup time to
WE21 EIM_WAIT hold time from
WE1
WE2
WE3
WE4
WE5
WE6
WE7
WE8
WE9
t is axi_clk cycle time. The maximum allowed axi_clk frequency is 133 MHz, whereas the maximum allowed EIM_BCLK
frequency is 66.5 MHz. As a result, if BCD = 0, axi_clk must be
resulting in a EIM_BCLK of 66.5 MHz. When the clock branch to EIM is decreased to 66.5 MHz, other buses are impacted
which are clocked from this source. See the CCM chapter of the MCIMX50 Applications Processor Reference Manual
(MCIMX50RM) for a detailed clock tree description.
ID
EIM_BCLK Cycle time
EIM_BCLK Low Level Width
EIM_BCLK High Level
Width
Clock rise to address valid
Clock rise to address invalid 0.5t – 1.25 0.5t + 1.75 t – 1.25 t + 1.75 2t – 1.25 2t + 1.75 3t – 1.25 3t + 1.75
Clock rise to EIM_CSx valid 0.5t – 1.25 0.5t + 1.75 t – 1.25 t + 1.75 2t – 1.25 2t + 1.75 3t – 1.25 3t + 1.75
Clock rise to EIM_CSx
invalid
Clock rise to EIM_RW valid
Clock rise to EIM_RW
invalid
invalid
invalid
valid
Invalid
Clock rise
Clock rise
Clock rise
Clock rise
Parameter
i.MX50 Applications Processors for Consumer Products, Rev. 4
2
3
0.5t – 1.25 0.5t + 1.75 t – 1.25 t + 1.75 2t – 1.25 2t + 1.75 3t – 1.25 3t + 1.75
0.5t – 1.25 0.5t + 1.75 t – 1.25 t + 1.75 2t – 1.25 2t + 1.75 3t – 1.25 3t + 1.75
0.5t – 1.25 0.5t + 1.75 t – 1.25 t + 1.75 2t – 1.25 2t + 1.75 3t – 1.25 3t + 1.75
0.5t – 1.25 0.5t + 1.75 t – 1.25 t + 1.75 2t – 1.25 2t + 1.75 3t – 1.25 3t + 1.75
0.5t – 1.25 0.5t + 1.75 t – 1.25 t + 1.75 2t – 1.25 2t + 1.75 3t – 1.25 3t + 1.75
0.5t – 1.25 0.5t + 1.75 t – 1.25 t + 1.75 2t – 1.25 2t + 1.75 3t – 1.25 3t + 1.75
0.5t – 1.25 0.5t + 1.75 t – 1.25 t + 1.75 2t – 1.25 2t + 1.75 3t – 1.25 3t + 1.75
0.5t – 1.25 0.5t + 1.75 t – 1.25 t + 1.75 2t – 1.25 2t + 1.75 2t – 1.25 2t + 1.75
0.5t – 1.25 0.5t + 1.75 t – 1.25 t + 1.75 2t – 1.25 2t + 1.75 2t – 1.25 2t + 1.75
Table 42. EIM Bus Timing Parameters
Min
0.4t
0.4t
2.5
2.5
2
2
t
BCD = 0
Max
—
—
—
—
—
—
—
≤
Min
0.8t
0.8t
2.5
2.5
2t
66.5 MHz. If BCD = 1, then 133 MHz is allowed for axi_clk,
2
2
BCD = 1
Max
—
—
—
—
—
—
—
1
Min
1.2t
1.2t
2.5
2.5
3t
2
2
BCD = 2
Max
—
—
—
—
—
—
—
Electrical Characteristics
Min
1.6t
1.6t
2.5
2.5
4t
2
2
BCD = 3
Max
—
—
—
—
—
—
—
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