MCIMX508CZK8B Freescale Semiconductor, MCIMX508CZK8B Datasheet - Page 29

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MCIMX508CZK8B

Manufacturer Part Number
MCIMX508CZK8B
Description
Processors - Application Specialized CODEX REV 1.1
Manufacturer
Freescale Semiconductor
Type
Multimedia Applicationsr
Datasheet

Specifications of MCIMX508CZK8B

Core
ARM Cortex A8
Processor Series
i.MX50

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4.2.1
Figure 2
4.2.2
The power-down sequence is recommended to be the opposite of the power-up sequence. In other words,
the same power supply constraints exist while powering off as while powering on.
4.2.3
When the i.MX50 is resuming from STOP mode, there are some special sequencing considerations. The
resume timing is determined by the following internal counters:
Freescale Semiconductor
1. STBY_COUNT. This register is in the CCM block and may be set to a maximum of 16 x 32 kHz
cycles, or 500 μsec.
shows the power-up sequence.
Power-Up Sequence
Power-Down Sequence
Resume Sequence
1) The POR_B input must be immediately asserted at power-up and remain
asserted until after the last power rail is at its working voltage.
2) No power-up sequence dependencies exist between the supplies shown
shaded in gray.
i.MX50 Applications Processors for Consumer Products, Rev. 4
Figure 2. Power-Up Sequence
NOTE
Electrical Characteristics
29

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