AT89LP51ED2-20MU Atmel, AT89LP51ED2-20MU Datasheet - Page 106

• Manufacturer Part Number: AT89LP51ED2-20MU
• Description: 8-bit Microcontrollers - MCU 64KB 20MHz 2.4V-5.5V
• Manufacturer: Atmel

Specifications of AT89LP51ED2-20MU

• Rohs: yes
• Core: 8051
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 64 KB
• Data Ram Size: 256 B
• On-chip Adc: Yes
• Operating Supply Voltage: 2.4 V to 5.5 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: VQFN-44
• Mounting Style: SMD/SMT
• Data Rom Size: 4 KB
• Interface Type: 2-Wire, SPI, UART
• Number Of Programmable I/os: 36
• Number Of Timers: 3
• Processor Series: AT89x
• Program Memory Type: Flash
• Factory Pack Quantity: 360

15.7
16. Hardware Watchdog Timer
106
PCA Watchdog Timer
AT89LP51RD2/ED2/ID2 Preliminary
An on-board watchdog timer is available with the PCA to improve the reliability of the system
without increasing chip count. Watchdog timers are useful for systems that are susceptible to
noise, power glitches, or electrostatic discharge. Module 4 is the only PCA module that can be
programmed as a watchdog. However, this module can still be used for other modes if the
watchdog is not needed.
pre-loads a 16-bit value in the compare registers. Just like the other compare modes, this 16-bit
value is compared to the PCA timer value. If a match is allowed to occur, an internal reset will be
generated. This reset will not cause the RST pin to be driven active.
In order to hold off the reset, the user has three options:
The first two options are more reliable because the watchdog timer is never disabled as in option
#3. If the program counter ever goes astray, a match will eventually occur and cause an internal
reset. The second option is also not recommended if other PCA modules are being used.
Remember, the PCA timer is the time base for all modules; changing the time base for other
modules would not be a good idea. Thus, in most applications the first solution is the best option.
This watchdog timer won’t generate a reset out on the reset pin. Only the Hardware Watchdog
can generate a board-level reset.
The programmable Hardware Watchdog Timer (WDT) protects the system from incorrect execu-
tion by triggering a system reset when it times out after the software has failed to feed the timer
prior to the timer overflow. Each WDT clock cycle depends on the Timer Prescaler (see
6.9 on page
caler bits, WTO0, WTO1 and WTO2 in SFR WDTPRG are used to set the period of the
Watchdog Timer from 16K to 2048K WDT clock cycles. The WDT is disabled by Reset and dur-
ing Power-down mode. When the WDT times out without being serviced, a RST pulse last 96
system clocks (48 system clocks in X2 Mode) is generated to reset the CPU. This reset is also
driven out on the RST pin (see
See
The Watchdog Timer consists of a 14-bit timer with 7-bit programmable prescaler. Writing the
sequence 1EH/E1H to the WDTRST register enables the timer. When the WDT is enabled, the
WDTEN bit in WDTPRG will be set to “1”. To prevent the WDT from generating a reset when if
overflows, the watchdog feed sequence must be written to WDTRST before the end of the time-
out period. To feed the watchdog, two write instructions must be sequentially executed success-
fully. Between the two write instructions, SFR reads are allowed, but writes are not allowed. The
instructions should move 1EH to the WDTRST register and then 1EH to the WDTRST register.
An incorrect feed or enable sequence will cause an immediate watchdog reset.
1. Periodically change the compare value so it will never match the PCA timer.
2. Periodically change the PCA timer value so it will never match the compare values.
3. Disable the watchdog by clearing the WDTE bit before a match occurs and then re-
Table 16-1
enable it.
50). By Default the WDT counts every 6 CPU clock cycles since TPS = 5. The pres-
for the available WDT period selections
Time-out Period
Figure 15-4
Section 7.4 on page
shows a diagram of how the watchdog works. The user
=
2
---------------------------- -
(
WTO
f
SYS
+
56) if the DISRTO bit in WDTPRG is not set.
14
)
×
(
TPS
+
1
)
3714A–MICRO–7/11
Section