AT89LP51ED2-20MU Atmel, AT89LP51ED2-20MU Datasheet - Page 56

• Manufacturer Part Number: AT89LP51ED2-20MU
• Description: 8-bit Microcontrollers - MCU 64KB 20MHz 2.4V-5.5V
• Manufacturer: Atmel

Specifications of AT89LP51ED2-20MU

• Rohs: yes
• Core: 8051
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 64 KB
• Data Ram Size: 256 B
• On-chip Adc: Yes
• Operating Supply Voltage: 2.4 V to 5.5 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: VQFN-44
• Mounting Style: SMD/SMT
• Data Rom Size: 4 KB
• Interface Type: 2-Wire, SPI, UART
• Number Of Programmable I/os: 36
• Number Of Timers: 3
• Processor Series: AT89x
• Program Memory Type: Flash
• Factory Pack Quantity: 360

7.4
7.5
7.6
56
Hardware Watchdog Reset
PCA Watchdog Reset
Software Reset
AT89LP51RD2/ED2/ID2 Preliminary
When the Hardware Watchdog times out, it will generate a reset pulse lasting 49 clock cycles.
By default this pulse is also output on the RST pin. The output pulse is either open-drain or
open-source as shown in
board in the case of an external capacitor or power-supply supervisor circuit, a 1 kΩ resistor
should be placed in series with any external driving circuitry as shown in
the RST output the DISRTO bit in the WDTPRG register must be set to one. Watchdog reset will
set the WDTOVF flag in WDTPRG. To prevent a Watchdog reset, the watchdog reset sequence
1EH/E1H must be written to WDTRST before the Watchdog times out. See
106
Figure 7-5.
Module 4 of the Programmable Counter Array (PCA) can be configured as a watchdog timer.
When a compare match occurs between module 4 and the PCA timer, it will generate an internal
reset pulse lasting 16 clock cycles. This pulse is never output on the RST pin. See
on page 106
The CPU may generate a 49-clock cycle reset pulse by writing the software reset sequence
5AH/A5H to the WDRST register. A software reset will set the SWRST bit in WDTPRG. See
“Software Reset” on page 107
other than 5AH/A5H or 1EH/E1H to WDTRST will generate an immediate reset and set both
WDTOVF and SWRST to flag an error. Software reset will also drive the RST pin active unless
DISRTO is set.
for details on the operation of the Watchdog.
Vcc
RST
Vcc
+
for details on the operation of the PCA Watchdog.
Recommended Reset Output Schematics
1 kΩ
Figure
RST
for more information on software reset. Writing any sequences
AT89LP51xD2
7-4. In order to properly propagate this pulse to the rest of the
To other
on-board
circuitry
POL = 1
Vcc
RST
+
1 kΩ
Figure
Section 16. on page
RST
AT89LP51xD2
7-5. To disable
3714A–MICRO–7/11
To other
on-board
circuitry
Section 15.7
POL = 0