AT89LP51ED2-20MU Atmel, AT89LP51ED2-20MU Datasheet - Page 130

• Manufacturer Part Number: AT89LP51ED2-20MU
• Description: 8-bit Microcontrollers - MCU 64KB 20MHz 2.4V-5.5V
• Manufacturer: Atmel

Specifications of AT89LP51ED2-20MU

• Rohs: yes
• Core: 8051
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 64 KB
• Data Ram Size: 256 B
• On-chip Adc: Yes
• Operating Supply Voltage: 2.4 V to 5.5 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: VQFN-44
• Mounting Style: SMD/SMT
• Data Rom Size: 4 KB
• Interface Type: 2-Wire, SPI, UART
• Number Of Programmable I/os: 36
• Number Of Timers: 3
• Processor Series: AT89x
• Program Memory Type: Flash
• Factory Pack Quantity: 360

18.1.5
130
AT89LP51RD2/ED2/ID2 Preliminary
Pin Configuration
If the SS pin is driven low by peripheral circuitry when the SPI is configured as a Master with
SSIG = 0, the SPI system interprets this as another master selecting the SPI as a slave and
starting to send data to it. To avoid bus contention, the SPI system takes the following actions:
Thus, when interrupt-driven SPI transmission is used in Master mode, and there exists a possi-
bility that SS may be driven low, the interrupt should always check that the MSTR bit is still set. If
the MSTR bit has been cleared by a slave select, it must be set by the user to re-enable SPI
Master mode.
When the SPI is enabled (SPEN = 1), the data direction of the MOSI, MISO and SCK pins is
automatically overridden according to the MSTR bit as shown in
reconfigure the pins when switching from master to slave or vice-versa. For more details on port
configuration, refer to
.
Table 18-2.
Notes:
1. The MSTR bit in SPCON is cleared and the SPI system becomes a Slave. As a result
2. The MODF Flag in SPSTA is set, and if the SPI interrupt is enabled, the interrupt rou-
MOSI
MISO
SCK
Pin
of the SPI becoming a Slave, the MOSI and SCK pins become inputs.
tine will be executed.
1. In these modes MOSI is active only during transfers. MOSI will be pulled high between trans-
2. In Push-Pull mode MOSI is active only during transfers, otherwise it is tristated to prevent line
fers to allow other masters to control the line.
contention. A weak external pull-up may be required to prevent MOSI from floating.
Mode
Quasi-bidirectional
Push-Pull Output
Input-Only
Open-Drain Output
Quasi-bidirectional
Push-Pull Output
Input-Only
Open-Drain Output
Quasi-bidirectional
Push-Pull Output
Input-Only
Open-Drain Output
SPI Pin Configuration and Behavior when SPE = 1
“Port Configuration” on page
Master (MSTR = 1)
Output
Output
No output (Tristated)
Output
Output
Output
No output (Tristated)
Output
Input (Internal Pull-up)
Input (Tristate)
Input (Tristate)
Input (External Pull-up)
(1)
(2)
(1)
71.
Slave (MSTR = 0)
Input (Internal Pull-up)
Input (Tristate)
Input (Tristate)
Input (External Pull-up)
Input (Internal Pull-up)
Input (Tristate)
Input (Tristate)
Input (External Pull-up)
Output (SS = 0)
Internal Pull-up (SS = 1)
Output (SS = 0)
Tristated (SS = 1)
No output (Tristated)
Output (SS = 0)
External Pull-up (SS = 1)
Table
18-2. The user need not
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