AT89LP51ED2-20MU Atmel, AT89LP51ED2-20MU Datasheet - Page 141

• Manufacturer Part Number: AT89LP51ED2-20MU
• Description: 8-bit Microcontrollers - MCU 64KB 20MHz 2.4V-5.5V
• Manufacturer: Atmel

Specifications of AT89LP51ED2-20MU

• Rohs: yes
• Core: 8051
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 64 KB
• Data Ram Size: 256 B
• On-chip Adc: Yes
• Operating Supply Voltage: 2.4 V to 5.5 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: VQFN-44
• Mounting Style: SMD/SMT
• Data Rom Size: 4 KB
• Interface Type: 2-Wire, SPI, UART
• Number Of Programmable I/os: 36
• Number Of Timers: 3
• Processor Series: AT89x
• Program Memory Type: Flash
• Factory Pack Quantity: 360

19.3
19.3.1
19.3.2
3714A–MICRO–7/11
Overview of the TWI Module
SCL and SDA Pins
Bit Rate Generator Unit
It is the user software’s responsibility to ensure that these illegal arbitration conditions never
occur. This implies that in multi-master systems, all data transfers must use the same composi-
tion of SLA+R/W and data packets. In other words: All transmissions must contain the same
number of data packets, otherwise the result of the arbitration is undefined.
The TWI module is comprised of several submodules, as shown in
drawn in a thick line are accessible through the AT89LP data bus.
Figure 19-9. Overview of the TWI Module
These pins interface the TWI with the rest of the MCU system. The output drivers contain a slew-
rate limiter in order to conform to the TWI specification. The input stages contain a spike sup-
pression unit removing spikes shorter than 50 ns.
This unit controls the period of SCL when operating in a Master mode. The SCL period is con-
trolled by settings in the SSCON register. Slave operation does not depend on the Bit Rate
setting, but the CPU clock frequency in the slave must be at least 16 times higher than the SCL
frequency. Note that slaves may prolong the SCL low period, thereby reducing the average TWI
bus clock period. The SCL frequency is generated according to
Address Match Unit
Slew-rate
Arbitration Detection
Control
START / STOP
Address Comparator
Address Register
Control
SCL
(SSADR)
Spike
Filter
Bus Interface Unit
AT89LP51RD2/ED2/ID2 Preliminary
Spike Suppression
Address/Data Shift
Register (SSDAT)
Slew-rate
Control
SDA
Status Register
Ack
Spike
Filter
(SSCS)
State Machine and
Control Unit
Status Control
Table
Control Register
Bit Rate Generator
(SSCON)
Figure
19-1.
Timer 1 Overflow
Prescaler
19-9. All registers
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