AT89LP51ED2-20MU Atmel, AT89LP51ED2-20MU Datasheet - Page 108

• Manufacturer Part Number: AT89LP51ED2-20MU
• Description: 8-bit Microcontrollers - MCU 64KB 20MHz 2.4V-5.5V
• Manufacturer: Atmel

Specifications of AT89LP51ED2-20MU

• Rohs: yes
• Core: 8051
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 64 KB
• Data Ram Size: 256 B
• On-chip Adc: Yes
• Operating Supply Voltage: 2.4 V to 5.5 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: VQFN-44
• Mounting Style: SMD/SMT
• Data Rom Size: 4 KB
• Interface Type: 2-Wire, SPI, UART
• Number Of Programmable I/os: 36
• Number Of Timers: 3
• Processor Series: AT89x
• Program Memory Type: Flash
• Factory Pack Quantity: 360

16.2
Table 16-2.
Table 16-3.
108
WDTPRG Address = A7H
Not Bit Addressable
Bit
Symbol
WDTOVF
SWRST
WDTEN
WDIDLE
DISRTO
WTO2
WTO1
WTO0
WDTCON Address = A6H
Not Bit Addressable
Bit
The WDT is enabled by writing the sequence 1EH/E1H to the WDTRST SFR. The current status may be checked by reading
the WDTEN bit in WDTCON. To prevent the WDT from resetting the device, the same sequence 1EH/E1H must be written to
WDTRST before the time-out interval expires. A software reset is generated by writing the sequence 5AH/A5H to WDTRST.
WDT Registers
WDTOVF
AT89LP51RD2/ED2/ID2 Preliminary
–
7
7
Function
Watchdog Overflow Flag
Set by hardware when a WDT rest is generated by the WDT timer overflow. Also set when an incorrect sequence is
written to WDTRST. Must be cleared by software.
Software Reset Flag
Set by hardware when a software reset is generated by writing the sequence 5AH/A5H to WDTRST. Also set when an
incorrect sequence is written to WDTRST. Must be cleared by software.
Watchdog Enable Flag
This bit is READ-ONLY and reflects the status of the WDT (whether it is running or not). The WDT is disabled after any
reset and must be re-enabled by writing 1EH/E1H to WDTRST
WDT Disable During Idle
When WDIDLE = 0 the WDT continues to count in Idle mode. When WDIDLE = 1 the WDT halts counting in Idle mode.
Disable Reset Output
When DISTRO = 0 the reset pin is driven to the same level as POL when the WDT resets. When DISRTO = 1 the reset
pin is input only.
Watchdog Tiemout
Prescaler bits for the watchdog timer (WDT). When all three bits are cleared to 0, the watchdog timer has a nominal
period of 16K clock cycles. When all three bits are set to 1, the nominal period is 2048K clock cycles.
WDTPRG – Watchdog Control Register
WDTRST – Watchdog Reset Register
SWRST
6
–
6
)
WDTEN
–
5
5
WDIDLE
4
–
4
DISRTO
–
3
3
WTO2
2
–
2
Reset Value = xx00 0000B
WTO1
1
–
1
(Write-Only)
WTO0
3714A–MICRO–7/11
0
–
0