AT89LP51ED2-20MU Atmel, AT89LP51ED2-20MU Datasheet - Page 135

• Manufacturer Part Number: AT89LP51ED2-20MU
• Description: 8-bit Microcontrollers - MCU 64KB 20MHz 2.4V-5.5V
• Manufacturer: Atmel

Specifications of AT89LP51ED2-20MU

• Rohs: yes
• Core: 8051
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 64 KB
• Data Ram Size: 256 B
• On-chip Adc: Yes
• Operating Supply Voltage: 2.4 V to 5.5 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: VQFN-44
• Mounting Style: SMD/SMT
• Data Rom Size: 4 KB
• Interface Type: 2-Wire, SPI, UART
• Number Of Programmable I/os: 36
• Number Of Timers: 3
• Processor Series: AT89x
• Program Memory Type: Flash
• Factory Pack Quantity: 360

Table 18-4.
Table 18-5.
3714A–MICRO–7/11
SPDAT Address = C5H
Not Bit Addressable
SPSTA Address = C4H
Not Bit Addressable
Symbol
SPIF
WCOL
SSERR
MODF
TXE
DORD
REMAP
TBIE
Bit
Bit
SPIF
SPD7
Function
SPI Transfer Complete Interrupt Flag
When a serial transfer is complete, the SPIF bit is set by hardware and an interrupt is generated if ESP = 1. The SPIF bit
may be cleared by software or by reading the SPI status register followed by reading/writing the SPI data register.
Write Collision Flag
The WCOL bit is set by hardware if SPDAT is written while the transmit buffer is full. The ongoing transfer is not affected.
WCOL may be cleared by software or by reading the SPI status register followed by reading/writing the SPI data register.
SS Slave Error Flag
Set by hardware when SS is deasserted before the end of a received data byte.
Mode Fault Flag
MODF is set by hardware when a master mode collision is detected (MSTR = 1, SSIG = 0 and SS = 0) and an interrupt
is generated if ESP = 1. MODF must be cleared by software.
Transmit Buffer Empty Flag
Set by hardware when the transmit buffer is loaded into the shift register, allowing a new byte to be loaded. TXE must be
cleared by software. When ENH = 1 and ESP = 1, TXE will generate an interrupt.
Data order
DORD = 1 selects LSB first data transmission. DORD = 0 selects MSB first data transmission.
Remap SPI Pins
When cleared the SPI pins are in the default locations on Port 1 that are compatible with AT89C51RD2/ED2/ID2. When
set the pins are shuffled on Port 1 to match the AT89S8253 or AT89LP6440 devices. See
TX Buffer Interrupt Enable
When TBIE = 1, TXE will generate an SPI interrupt if ESP = 1. When TBIE = 0, TXE does not generate an interrupt.
7
7
SPDAT – SPI Data Register
SPSTA – SPI Status Register
WCOL
SPD6
6
6
SSERR
SPD5
5
5
MODF
SPD4
4
4
AT89LP51RD2/ED2/ID2 Preliminary
SPD3
TXE
3
3
DORD
SPD2
2
2
Reset Value = 0000 0000
Reset Value = 0000 0000B
REMAP
SPD1
1
Table
1
18-1.
SPD0
TBIE
0
0
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