MA330028 Microchip Technology, MA330028 Datasheet - Page 121

• Manufacturer Part Number: MA330028
• Description: Daughter Cards & OEM Boards dsPIC33EP64MC504 PIM
• Manufacturer: Microchip Technology

Specifications of MA330028

• Rohs: yes
• Product: Daughter Cards
• Core: dsPIC
• Description/function: Plug-in-module with dsPIC33EP64MC504 device for use with DM330021 and DM330023 motor control development board
• Interface Type: CAN, I2C, SPI
• Operating Supply Voltage: 3 to 3.6 V
• Tool Is For Evaluation Of: dsPIC33EP64MC504
• For Use With: DM330021, DM330023

6.0
The Reset module combines all reset sources and
controls the device Master Reset Signal, SYSRST. The
following is a list of device Reset sources:
• POR: Power-on Reset
• BOR: Brown-out Reset
• MCLR: Master Clear Pin Reset
• SWR: RESET Instruction
• WDTO: Watchdog Timer Reset
• CM: Configuration Mismatch Reset
• TRAPR: Trap Conflict Reset
• IOPUWR: Illegal Condition Device Reset
FIGURE 6-1:
© 2011-2012 Microchip Technology Inc.
- Illegal Opcode Reset
- Uninitialized W Register Reset
- Security Reset
Note 1: This data sheet summarizes the features
2: Some registers and associated bits
RESETS
of
dsPIC33EPXXXMC20X/50X,
PIC24EPXXXGP/MC20X
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 8. “Reset”
(DS70602) of the “dsPIC33E/PIC24E
Family Reference Manual”, which is
available from the Microchip web site
(www.microchip.com).
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization”
this data sheet for device-specific register
and bit information.
MCLR
V
DD
Uninitialized W Register
the
Configuration Mismatch
RESET SYSTEM BLOCK DIAGRAM
Regulator
RESET Instruction
Internal
Sleep or Idle
Security Reset
Module
Illegal Opcode
dsPIC33EPXXXGP50X,
WDT
Trap Conflict
V
families
Detect
DD
Glitch Filter
Rise
and
Preliminary
BOR
POR
of
in
A simplified block diagram of the Reset module is
shown in
Any active source of Reset will make the SYSRST sig-
nal active. On system Reset, some of the registers
associated with the CPU and peripherals are forced to
a known Reset state and some are unaffected.
All types of device Reset sets a corresponding status
bit in the RCON register to indicate the type of Reset
(see
A POR clears all the bits, except for the POR and BOR
bits (RCON<1:0>), that are set. The user application
can set or clear any bit at any time during code
execution. The RCON bits only serve as status bits.
Setting a particular Reset status bit in software does
not cause a device Reset to occur.
The RCON register also has other bits associated with
the Watchdog Timer and device power-saving states.
The function of these bits is discussed in other sections
of this manual.
There are two types of Reset, a cold Reset and a warm
Reset. A cold Reset is the result of a POR or BOR and
the FNOSC Configuration bits in the FOSC device
Configuration register select the device clock source. A
warm Reset is the result of all other Resets including
the RESET instruction and the Current Oscillator Selec-
tion bits (COSC<2:0>) in the Oscillator Control register
(OSCCON<14:12>) select the clock source.
Note:
Note:
Register
Figure
Refer to the specific peripheral section or
Section 4.0 “Memory Organization”
this manual for register Reset states.
The status bits in the RCON register
should be cleared after they are read so
that the next RCON register value after a
device Reset is meaningful.
6-1).
6-1.
SYSRST
DS70657E-page 121
of