MA330028 Microchip Technology, MA330028 Datasheet - Page 141

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MA330028

Manufacturer Part Number
MA330028
Description
Daughter Cards & OEM Boards dsPIC33EP64MC504 PIM
Manufacturer
Microchip Technology
Datasheet

Specifications of MA330028

Rohs
yes
Product
Daughter Cards
Core
dsPIC
Description/function
Plug-in-module with dsPIC33EP64MC504 device for use with DM330021 and DM330023 motor control development board
Interface Type
CAN, I2C, SPI
Operating Supply Voltage
3 to 3.6 V
Tool Is For Evaluation Of
dsPIC33EP64MC504
For Use With
DM330021, DM330023

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MA330028
Manufacturer:
MICROCHIP
Quantity:
12 000
REGISTER 8-2:
© 2011-2012 Microchip Technology Inc.
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14-8
bit 7-0
Note 1:
FORCE
R/W-0
R/S-0
2:
(1)
The FORCE bit cannot be cleared by user software. The FORCE bit is cleared by hardware when the
forced DMA transfer is complete or the channel is disabled (CHEN = 0).
This selection is available in dsPIC33EPXXXGP/MC50X devices only.
FORCE: Force DMA Transfer bit
1 = Force a single DMA transfer (Manual mode)
0 = Automatic DMA transfer initiation by DMA Request
Unimplemented: Read as
IRQSEL<7:0>: DMA Peripheral IRQ Number Select bits
01000110 = ECAN1 – TX Data Request
00100110 = IC4 – Input Capture 4
00100101 = IC3 – Input Capture 3
00100010 = ECAN1 – RX Data Ready
00100001 = SPI2 Transfer Done
00011111 = UART2TX – UART2 Transmitter
00011110 = UART2RX – UART2 Receiver
00011100 = TMR5 – Timer5
00011011 = TMR4 – Timer4
00011010 = OC4 – Output Compare 4
00011001 = OC3 – Output Compare 3
00001101 = ADC1 – ADC1 Convert done
00001100 = UART1TX – UART1 Transmitter
00001011 = UART1RX – UART1 Receiver
00001010 = SPI1 – Transfer Done
00001000 = TMR3 – Timer3
00000111 = TMR2 – Timer2
00000110 = OC2 – Output Compare 2
00000101 = IC2 – Input Capture 2
00000010 = OC1 – Output Compare 1
00000001 = IC1 – Input Capture 1
00000000 = INT0 – External Interrupt 0
R/W-0
U-0
DMA
X
REQ: DMA CHANNEL
‘1’ = Bit is set
W = Writable bit
R/W-0
U-0
0
R/W-0
(1)
U-0
Preliminary
IRQSEL<7:0>
(2)
X
(2)
IRQ SELECT REGISTER
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/W-0
U-0
R/W-0
U-0
x = Bit is unknown
R/W-0
U-0
DS70657E-page 141
R/W-0
U-0
bit 8
bit 0

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