MA330028 Microchip Technology, MA330028 Datasheet - Page 138

• Manufacturer Part Number: MA330028
• Description: Daughter Cards & OEM Boards dsPIC33EP64MC504 PIM
• Manufacturer: Microchip Technology

Specifications of MA330028

• Rohs: yes
• Product: Daughter Cards
• Core: dsPIC
• Description/function: Plug-in-module with dsPIC33EP64MC504 device for use with DM330021 and DM330023 motor control development board
• Interface Type: CAN, I2C, SPI
• Operating Supply Voltage: 3 to 3.6 V
• Tool Is For Evaluation Of: dsPIC33EP64MC504
• For Use With: DM330021, DM330023

In addition, DMA transfers can be triggered by Timers
as well as external interrupts. Each DMA channel is
unidirectional. Two DMA channels must be allocated to
read and write to a peripheral. If more than one channel
receive a request to transfer data, a simple fixed priority
scheme, based on channel number, dictates which
channel completes the transfer and which channel, or
channels, are left pending. Each DMA channel moves
a block of data, after which it generates an interrupt to
the CPU to indicate that the block is available for
processing.
The
capabilities:
• Four DMA channels
• Register Indirect With Post-increment Addressing
• Register Indirect Without Post-increment
TABLE 8-1:
DS70657E-page 138
INT0 – External Interrupt 0
IC1 – Input Capture 1
IC2 – Input Capture 2
IC3 – Input Capture 3
IC4 – Input Capture 4
OC1 – Output Compare 1
OC2 – Output Compare 2
OC3 – Output Compare 3
OC4 – Output Compare 4
TMR2 – Timer2
TMR3 – Timer3
TMR4 – Timer4
TMR5 – Timer5
SPI1 Transfer Done
SPI2 Transfer Done
UART1RX – UART1 Receiver
UART1TX – UART1 Transmitter
UART2RX – UART2 Receiver
UART2TX – UART2 Transmitter
ECAN1 – RX Data Ready
ECAN1 – TX Data Request
ADC1 – ADC1 Convert Done
Peripheral to DMA Association
mode
Addressing mode
DMA
controller
DMA CHANNEL TO PERIPHERAL ASSOCIATIONS
provides
these
DMAxREQ Register
IRQSEL<7:0> Bits
00000000
00000001
00000101
00100101
00100110
00000010
00000110
00011001
00011010
00000111
00001000
00011011
00011100
00001010
00100001
00001011
00001100
00011110
00011111
00100010
01000110
00001101
functional
Preliminary
• Peripheral Indirect Addressing mode (peripheral
• CPU interrupt after half or full-block transfer com-
• Byte or word transfers
• Fixed priority channel arbitration
• Manual (software) or Automatic (peripheral DMA
• One-Shot or Auto-Repeat block transfer modes
• Ping-Pong mode (automatic switch between two
• DMA request for each channel can be selected
• Debug support features
The peripherals that can utilize DMA are listed in
Table
(Values to Read from
0x0300 (ADC1BUF0)
generates destination address)
plete
requests) transfer initiation
SRAM start addresses after each block transfer
complete)
from any supported interrupt source
DMAxPAD Register
0x0226 (U1RXREG)
0x0236 (U2RXREG)
0x0248 (SPI1BUF)
0x0268 (SPI2BUF)
0x014C (IC2BUF)
0x015C (IC4BUF)
0x0144 (IC1BUF)
0x0154 (IC3BUF)
0x0440 (C1RXD)
8-1.
Peripheral)
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© 2011-2012 Microchip Technology Inc.
DMAxPAD Register
0x0224 (U1TXREG)
0x0234 (U2TXREG)
(Values to Write to
0x0248 (SPI1BUF)
0x0268 (SPI2BUF)
0x090E (OC2RS)
0x0904 (OC1RS)
0x0918 (OC3RS)
0x0922 (OC4RS)
0x0442 (C1TXD)
0x091A (OC3R)
0x0906 (OC1R)
0x0910 (OC2R)
0x0924 (OC4R)
Peripheral)
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