MT48LC16M8A2P-75:G Micron Technology Inc, MT48LC16M8A2P-75:G Datasheet - Page 25

• Manufacturer Part Number: MT48LC16M8A2P-75:G
• Description: IC SDRAM 128MBIT 133MHZ 54TSOP
• Manufacturer: Micron Technology Inc
• Type: SDRAMr

Specifications of MT48LC16M8A2P-75:G

• Format - Memory: RAM
• Memory Type: SDRAM
• Memory Size: 128M (16M x 8)
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 54-TSOP II
• Organization: 16Mx8
• Density: 128Mb
• Address Bus: 14b
• Access Time (max): 6/5.4ns
• Maximum Clock Rate: 133MHz
• Operating Supply Voltage (typ): 3.3V
• Package Type: TSOP-II
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 150mA
• Pin Count: 54
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 9:
Figure 10:
Reads
PDF: 09005aef8091e66d/Source: 09005aef8091e625
128MSDRAM_2.fm - Rev. N 1/09 EN
Activating a Specific Row in a Specific Bank
Example: Meeting
READ bursts are initiated with a READ command, as shown in Figure 11 on page 26.
The starting column and bank addresses are provided with the READ command, and
auto precharge either is enabled or disabled for that burst access. If auto precharge is
enabled, the row being accessed is precharged at the completion of the burst. For the
generic READ commands used in the following illustrations, auto precharge is disabled.
During READ bursts, the valid data-out element from the starting column address will
be available following the CL after the READ command. Each subsequent data-out
element will be valid by the next positive clock edge. Figure 12 on page 26 shows general
timing for each possible CL setting.
Upon completion of a burst, assuming no other commands have been initiated, the DQ
will go High-Z. A full-page burst will continue until terminated. (At the end of the page, it
will wrap to column 0 and continue.)
COMMAND
A0–A10, A11
BA0, BA1
CLK
RAS#
CAS#
WE#
CKE
CLK
CS#
t
RCD (MIN) When 2 <
ACTIVE
T0
HIGH
NOP
T1
ADDRESS
25
ADDRESS
BANK
ROW
t
RCD
t
RCD (MIN)/
DON’T CARE
Micron Technology, Inc., reserves the right to change products or specifications without notice.
T2
NOP
t
CK ≤ 3
READ or
WRITE
128Mb: x4, x8, x16 SDRAM
T3
DON’T CARE
©1999 Micron Technology, Inc. All rights reserved.
T4
Operations