MT48LC16M8A2P-75:G Micron Technology Inc, MT48LC16M8A2P-75:G Datasheet - Page 53

IC SDRAM 128MBIT 133MHZ 54TSOP

MT48LC16M8A2P-75:G

Manufacturer Part Number
MT48LC16M8A2P-75:G
Description
IC SDRAM 128MBIT 133MHZ 54TSOP
Manufacturer
Micron Technology Inc
Type
SDRAMr
Datasheet

Specifications of MT48LC16M8A2P-75:G

Format - Memory
RAM
Memory Type
SDRAM
Memory Size
128M (16M x 8)
Speed
133MHz
Interface
Parallel
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Package / Case
54-TSOP II
Organization
16Mx8
Density
128Mb
Address Bus
14b
Access Time (max)
6/5.4ns
Maximum Clock Rate
133MHz
Operating Supply Voltage (typ)
3.3V
Package Type
TSOP-II
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Supply Current
150mA
Pin Count
54
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MT48LC16M8A2P-75:G
Manufacturer:
ST
Quantity:
2 000
Timing Diagrams
Figure 37:
PDF: 09005aef8091e66d/Source: 09005aef8091e625
128MSDRAM_2.fm - Rev. N 1/09 EN
DQML, DQMH
COMMAND
A0–A9, A11
BA0, BA1
DQM /
CKE
A10
CLK
DQ
T = 100µs
(
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Power-up:
V
CLK stable
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Initialize and Load Mode Register
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MIN
DD
and
t CKS
t CMS
Notes:
T0
NOP
t CKH
High-Z
t CMH
1. If CS# is HIGH at clock HIGH time, all commands applied are NOP.
2. The mode register may be loaded prior to the AUTO REFRESH cycles if desired.
3. JEDEC and PC100 specify 3 clocks.
4. Outputs are guaranteed High-Z after command is issued.
SINGLE BANK
t CMS
ALL BANKS
t CK
BANKS
PRECHARGE
ALL
T1
t CMH
t RP
Precharge
all banks
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t CMS
Tn + 1
REFRESH
AUTO
t CMH
t CH
AUTO REFRESH
t RFC
NOP
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NOP
53
t CL
To + 1
REFRESH
AUTO
AUTO REFRESH
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t RFC
NOP
(
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NOP
128Mb: x4, x8, x16 SDRAM
t AS
t AS
LOAD MODE
Tp + 1
REGISTER
CODE
CODE
t AH
t AH
Program Mode Register
©1999 Micron Technology, Inc. All rights reserved.
t MRD
Timing Diagrams
Tp + 2
NOP
2, 3, 4
Tp + 3
ACTIVE
BANK
ROW
ROW
DON’T CARE

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