MT46V64M16TG-6T IT:A TR Micron Technology Inc, MT46V64M16TG-6T IT:A TR Datasheet - Page 51

• Manufacturer Part Number: MT46V64M16TG-6T IT:A TR
• Description: IC DDR SDRAM 1GBIT 6NS 66TSOP
• Manufacturer: Micron Technology Inc
• Type: DDR SDRAMr

Specifications of MT46V64M16TG-6T IT:A TR

• Format - Memory: RAM
• Memory Type: DDR SDRAM
• Memory Size: 1G (64M x 16)
• Speed: 6ns
• Interface: Parallel
• Voltage - Supply: 2.3 V ~ 2.7 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 66-TSOP
• Organization: 64Mx16
• Density: 1Gb
• Address Bus: 16b
• Access Time (max): 700ps
• Maximum Clock Rate: 333MHz
• Operating Supply Voltage (typ): 2.5V
• Package Type: TSOP
• Operating Temp Range: -40C to 85C
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.3V
• Supply Current: 275mA
• Pin Count: 66
• Mounting: Surface Mount
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 24:
READ
PDF: 09005aef80a2f898/Source: 09005aef82a95a3a
DDR_x4x8x16_Core2.fm - 1Gb DDR: Rev. I, Core DDR: Rev. B 12/07 EN
Command
BA0, BA1
Address
CK#
CK
Example: Meeting
Bank x
Row
ACT
T0
Note:
During the READ command, the value on input A10 determines whether or not auto
precharge is used. If auto precharge is selected, the row being accessed will be
precharged at the end of the READ burst; if auto precharge is not selected, the row will
remain open for subsequent accesses.
During READ bursts, the valid data-out element from the starting column address will
be available following the CL after the READ command. Each subsequent data-out
element will be valid nominally at the next positive or negative clock edge (that is, at the
next crossing of CK and CK#). Figure 25 on page 53 shows the general timing for each
possible CL setting. DQS is driven by the DDR SDRAM along with output data. The
initial LOW state on DQS is known as the read preamble; the LOW state coincident with
the last data-out element is known as the read postamble.
Upon completion of a burst, assuming no other commands have been initiated, the DQ
will go High-Z. Detailed explanations of
window hold), and the valid data window are depicted in Figure 33 on page 61 and
Figure 34 on page 62. Detailed explanations of
t
Data from any READ burst may be concatenated or truncated with data from a subse-
quent READ command. In either case, a continuous flow of data can be maintained. The
first data element from the new burst follows either the last element of a completed
burst or the last desired data element of a longer burst which is being truncated. The
new READ command should be issued x cycles after the first READ command, where x
equals the number of desired data element pairs (pairs are required by the 2n-prefetch
architecture). This is shown in Figure 26 on page 54. A READ command can be initiated
on any clock cycle following a previous READ command. Nonconsecutive read data is
illustrated in Figure 27 on page 55. Full-speed random read accesses within a page (or
pages) can be performed, as shown in Figure 28 on page 56.
AC (data-out transition skew to CK) are depicted in Figure 35 on page 63.
NOP
For the READ commands used in the following illustrations, auto precharge is dis-
abled.
T1
t RRD
t
RCD (
NOP
t
RRD) MIN When 2 <
T2
Bank y
ACT
Row
51
T3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
t
RCD (
DQSQ (valid data-out skew),
NOP
T4
t
t
DQSCK (DQS transition skew to CK) and
RRD) MIN/
t RCD
1Gb: x4, x8, x16 DDR SDRAM
NOP
T5
t
CK ≤ 3
©2003 Micron Technology, Inc. All rights reserved.
RD/WR
Bank y
T6
Col
t
QH (data-out
Operations
Don’t Care
NOP
T7