MT46V64M16TG-6T IT:A TR Micron Technology Inc, MT46V64M16TG-6T IT:A TR Datasheet - Page 71

• Manufacturer Part Number: MT46V64M16TG-6T IT:A TR
• Description: IC DDR SDRAM 1GBIT 6NS 66TSOP
• Manufacturer: Micron Technology Inc
• Type: DDR SDRAMr

Specifications of MT46V64M16TG-6T IT:A TR

• Format - Memory: RAM
• Memory Type: DDR SDRAM
• Memory Size: 1G (64M x 16)
• Speed: 6ns
• Interface: Parallel
• Voltage - Supply: 2.3 V ~ 2.7 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 66-TSOP
• Organization: 64Mx16
• Density: 1Gb
• Address Bus: 16b
• Access Time (max): 700ps
• Maximum Clock Rate: 333MHz
• Operating Supply Voltage (typ): 2.5V
• Package Type: TSOP
• Operating Temp Range: -40C to 85C
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.3V
• Supply Current: 275mA
• Pin Count: 66
• Mounting: Surface Mount
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 43:
PDF: 09005aef80a2f898/Source: 09005aef82a95a3a
DDR_x4x8x16_Core2.fm - 1Gb DDR: Rev. I, Core DDR: Rev. B 12/07 EN
Command
Address
t DQSS (NOM)
t DQSS (MIN)
t DQSS (MAX)
DQS
DQS
DQS
CK#
DM
DM
DM
DQ
DQ
DQ
CK
WRITE-to-PRECHARGE – Uninterrupting
Notes:
Bank a,
WRITE
Col b
T0
t DQSS
t DQSS
t DQSS
1. DI b = data-in for column b.
2. Three subsequent elements of data-in are applied in the programmed order following DI b.
3. An uninterrupted burst of 4 is shown.
4.
5. The PRECHARGE and WRITE commands are to the same device. However, the PRECHARGE
6. A10 is LOW with the WRITE command (auto precharge is disabled).
t
and WRITE commands may be to different devices, in which case
the PRECHARGE command could be applied earlier.
WR is referenced from the first positive CK edge after the last data-in pair.
DI
b
NOP
DI
T1
b
DI
b
T1n
NOP
T2
T2n
71
NOP
T3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t WR
NOP
T4
1Gb: x4, x8, x16 DDR SDRAM
Transitioning Data
(a or all)
Bank,
T5
PRE
©2003 Micron Technology, Inc. All rights reserved.
t
WR is not required, and
t RP
Operations
T6
NOP
Don’t Care