MT28F320J3RG-11 GMET Micron Technology Inc, MT28F320J3RG-11 GMET Datasheet - Page 24

• Manufacturer Part Number: MT28F320J3RG-11 GMET
• Description: IC FLASH 32MBIT 110NS 56TSOP
• Manufacturer: Micron Technology Inc

Specifications of MT28F320J3RG-11 GMET

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 32M (4Mx8, 2Mx16)
• Speed: 110ns
• Interface: Parallel
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 56-TSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Table 17: Status Register Definitions
09005aef80b5a323
MT28F640J3.fm – Rev. N 3/05 EN
HIGH-Z
BUSY?
WHEN
ISMS
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
7
SR7 = WRITE STATE MACHINE STATUS (ISMS)
SR6 = ERASE SUSPEND STATUS (ESS)
SR5 = ERASE AND CLEAR LOCK BITS STATUS (ECLBS)
SR4 = PROGRAM AND SET LOCK BIT STATUS (PSLBS)
SR3 = PROGRAMMING VOLTAGE STATUS (V
SR2 = PROGRAM SUSPEND STATUS (PSS)
SR1 DEVICE PROTECTSTATUS (DPS)
SR0 = RESERVED FOR FUTURE ENHANCEMENTS
1 = Ready
0 = Busy
1 = Block Erase Suspended
0 = Block Erase in Progress/Completed
1 = Error in Block Erasure or Clear Block Bits
0 = Successful Block Erase or Clear Lock Bits
1 = Error in Programming or Setting Block Lock Bits
0 = Successful Program or Set Block Lock Bits
1 = Low Programming Voltage Detected,
0 = Programming Voltage OK
1 = Program Suspended
0 = Program in Progress/Completed
1 = Block Lock Bit Detected, Operation Aborted
0 = Unlock
ESS
6
Operation Aborted
STATUS REGISTER BITS
ECLBS
5
PSLBS
4
PENS
24
)
V
PENS
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Check STS or SR7 to determine block erase,
program, or lock bit configuration
completion. SR6–SR0 are not driven while
SR7 = 0.
If both SR5 and SR4 are “1s” after a block
erase, program, writer buffer command, or
lock bit configuration attempt, an improper
command sequence was entered.
SR3 does not provide a continuous voltage
level indication. The ISM interrogates and
indicates the programming voltage level
only after block erase, program, set block
lock bits, or clear block lock bits command
sequences.
SR1 does not provide a continuous
indication of block lock bit values. The ISM
interrogates the block lock bits only after
block erase, program, or lock bit
configuration command sequences. It
informs the system, depending on the
attempted operation, if the block lock bit is
set. Read the block lock configuration codes
using the READ IDENTIFIER CODES command
to determine block lock bits status. SR0 is
reserved for future use and should be
masked when polling the status register.
PSS
2
128Mb, 64Mb, 32Mb
Q-FLASH MEMORY
NOTES
DPS
1
©2000 Micron Technology. Inc.
R
0