MT28F320J3RG-11 GMET Micron Technology Inc, MT28F320J3RG-11 GMET Datasheet - Page 26

• Manufacturer Part Number: MT28F320J3RG-11 GMET
• Description: IC FLASH 32MBIT 110NS 56TSOP
• Manufacturer: Micron Technology Inc

Specifications of MT28F320J3RG-11 GMET

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 32M (4Mx8, 2Mx16)
• Speed: 110ns
• Interface: Parallel
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 56-TSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

WRITE-to-BUFFER Command
to program the Flash device via the write buffer. A
buffer can be loaded with a variable number of bytes,
up to the buffer size, before writing to the Flash device.
First, the WRITE-to-BUFFER SETUP command is
issued, along with the block address (see Figure 9 on
page 31). Then, the extended status register (XSR; see
Table 18) information is loaded and XSR7 indicates
“buffer available” status. If XSR7 = 0, the write buffer is
not available. To retry, issue the Write-to-Buffer setup
command with the block address and continue moni-
toring XSR7 until XSR7 = 1. When XSR7 transitions to
“1,” the buffer is ready for loading new data. Then the
part is given a word/byte count with the block address.
On the next write, a device start address is given, along
with the write buffer data. Depending on the count,
subsequent writes provide additional device addresses
and data. All subsequent addresses must lie within the
start address plus the count.
parallel. Due to this parallel programming, maximum
programming performance and lower power are
obtained by aligning the start address at the beginning
of a write buffer boundary (i.e., A0–A4 of the start
address = 0).
FIRM command is issued, thus programming the ISM
to begin copying the buffer data to the Flash array. If
Table 18: Extended Status Register Definitions (XSR)
NOTE:
09005aef80b5a323
MT28F640J3.fm – Rev. N 3/05 EN
HIGH-Z WHEN
BUSY?
The write-to-buffer command sequence is initiated
The device internally programs many Flash cells in
When the final buffer data is given, a WRITE CON-
To access the XSR data, issue only a READ to the device.
WBS
Yes
7
No
XSR7 = WRITE BUFFER STATUS (WBS)
XSR6–XSR0 = RESERVED FOR FUTURE ENHANCEMENTS
1 = Write Buffer Available
0 = Write Buffer Not Available
STATUS REGISTER BITS
26
RESERVED
the device receives a command other than WRITE
CONFIRM, an invalid command/sequence error is
generated and status register bits SR5 and SR4 are set
to “1.” For additional BUFFER WRITEs, issue another
WRITE-to-BUFFER SETUP command and check XSR7.
writing, and status register bit SR4 is set to a “1” to
indicate a program failure. The ISM only detects errors
for “1s” that do not successfully program to “0s.” When
a program error is detected, the status register should
be cleared. Note that the device does not accept any
more WRITE-to-BUFFER commands any time SR4
and/or SR5 is set. In addition, if the user attempts to
program past an erase block boundary with a WRITE-
to-BUFFER command, the device aborts the WRITE-
to-BUFFER operation and generates an invalid com-
mand/sequence error, and status register bits SR5 and
SR4 are set to “1.”
V
while V
are set to “1.” Buffered write attempts with invalid V
and V
should not be attempted. Finally, the corresponding
block lock bit should be reset for successful program-
ming. When a BUFFERED WRITE is attempted while
the corresponding block lock bit is set, SR1 and SR4 are
set to “1.”
PEN
If an error occurs during a write, the device stops
Reliable BUFFERED WRITEs can only occur when
6–0
Micron Technology, Inc., reserves the right to change products or specifications without notice.
= V
PEN
PEN
PENH
≤ V
voltages produce spurious results and
NOTES
After a BUFFER WRITE command, ZXSR7 = 1
indicates that a write buffer is available.
SR6–SR0 are reserved for future use and
should be masked when polling the status
register.
. If a BUFFERED WRITE is attempted
PENLK
128Mb, 64Mb, 32Mb
, status register bits SR4 and SR3
Q-FLASH MEMORY
©2000 Micron Technology. Inc.
CC