TE28F640J3C115SL7HA Intel, TE28F640J3C115SL7HA Datasheet - Page 36

• Manufacturer Part Number: TE28F640J3C115SL7HA
• Description: IC FLASH 64MBIT 115NS 56TSOP
• Manufacturer: Intel

Specifications of TE28F640J3C115SL7HA

• Format - Memory: FLASH
• Memory Type: StrataFlash® FLASH
• Memory Size: 64M (8Mx8, 4Mx16)
• Speed: 115ns
• Interface: Parallel
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 56-TSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 860794

256-Mbit J3 (x8/x16)
36
Clear Block Lock-Bits
Protection Program
NOTES:
10.The number of bytes/words to be written to the Write Buffer = N + 1, where N = byte/word count argument. Count ranges on
12.Attempts to issue a block erase or program to a locked block.
13.Either 0x40 or 0x10 are recognized by the WSM as the byte/word program setup.
14.Program suspends can be issued after either the Write-to-Buffer or Word/Byte-Program operation is initiated.
15.The clear block lock-bits operation simultaneously clears all block lock-bits.
11.The write to buffer or erase operation does not begin until a Confirm command (0xD0) is issued.
1. Commands other than those shown above are reserved by Intel for future device implementations and should not be used.
2. The Basic Command Set (BCS) is the same as the 28F008SA Command Set or Intel Standard Command Set. The Scalable
3. Bus operations are defined in
4. X = Any valid address within the device.
5. ID = Data read from Identifier Codes.
6. The upper byte of the data bus (D[15:8]) during command writes is a “Don’t Care” in x16 operation.
7. Following the Read Identifier Codes command, read operations access manufacturer, device and block lock codes. See
8. If the WSM is running, only D7 is valid; D[15:8] and D[6:0] float, which places them in a high-impedance state.
9. After the Write to Buffer command is issued check the XSR to make sure a buffer is available for writing.
Command Set (SCS) is also referred to as the Intel Extended Command Set.
BA = Address within the block.
IA = Identifier Code Address: see
QA = Query database Address.
PA = Address of memory location to be programmed.
RCD = Data to be written to the read configuration register. This data is presented to the device on A[16:1]; all other address
inputs are ignored.
QD = Data read from Query database.
SRD = Data read from Status Register. See
PD = Data to be programmed at location PA. Data is latched on the rising edge of WE#.
CC = Configuration Code.
Section 10.2
this device for byte mode are N = 00H to N = 1FH and for word mode are N = 0x00 to N = 0x0F. The third and consecutive
bus cycles, as determined by N, are for writing data into the Write Buffer. The Confirm command (0xD0) is expected after
exactly N + 1 write cycles; any other command at that point in the sequence aborts the write to buffer operation. See
18, “Write to Buffer Flowchart” on page 59
Table 14. Command Bus-Cycle Definitions (Sheet 2 of 2)
Command
for read identifier code data.
Scalable or
Command
Basic
Set
SCS
(2)
Table
Table
12.
Cycles
Req’d.
Bus
17.
2
2
for additional information
Table 18
Oper
Write
Write
(3)
for a description of the Status Register bits.
First Bus Cycle
Addr
X
X
(4)
Data
0xC0
0x60
(5,6)
Oper
Write
Write
(3)
Second Bus Cycle
Addr
PA
X
(4)
Data
0xD0
PD
(5,6)
Datasheet
Figure
Notes
1,15
1