FAN3100CMPX Fairchild Semiconductor, FAN3100CMPX Datasheet - Page 14

• Manufacturer Part Number: FAN3100CMPX
• Description: IC GATE DRVR SGL CMOS 2A 6MLP
• Manufacturer: Fairchild Semiconductor
• Type: Low Sider

Specifications of FAN3100CMPX

• Configuration: Low-Side
• Input Type: Differential
• Delay Time: 15ns
• Current - Peak: 3A
• Number Of Configurations: 1
• Number Of Outputs: 1
• Voltage - Supply: 4.5 V ~ 18 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 6-MLP
• Rise Time: 20 ns
• Fall Time: 14 ns
• Supply Voltage (min): 4.5 V
• Supply Current: 0.35 mA
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Number Of Drivers: 1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• High Side Voltage - Max (bootstrap): -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: FAN3100CMPXTR

© 2007 Fairchild Semiconductor Corporation
FAN3100 • Rev. 1.0.3
Applications Information
Input Thresholds
The FAN3100 offers TTL or CMOS input thresholds. In
the FAN3100T, the input thresholds meet industry-
standard TTL logic thresholds, independent of the V
voltage,
approximately 0.4V. These levels permit the inputs to be
driven from a range of input logic signal levels for which
a voltage over 2V is considered logic high. The driving
signal for the TTL inputs should have fast rising and
falling edges with a slew rate of 6V/µs or faster, so the
rise time from 0 to 3.3V should be 550ns or less. With
reduced slew rate, circuit noise could cause the driver
input voltage to exceed the hysteresis voltage and
retrigger the driver input, causing erratic operation.
In the FAN3100C, the logic input thresholds are
dependent on the V
logic rising edge threshold is approximately 55% of V
and the input falling edge threshold is approximately
38% of V
hysteresis voltage of approximately 17% of V
CMOS inputs can be used with relatively slow edges
(approaching DC) if good decoupling and bypass
techniques are incorporated in the system design to
prevent noise from violating the input voltage hysteresis
window. This allows setting precise timing intervals by
fitting an R-C circuit between the controlling signal and
the IN pin of the driver. The slow rising edge at the IN
pin of the driver introduces a delay between the
controlling signal and the OUT pin of the driver.
Static Supply Current
In the I
Figure 10 and Figure 15 - Figure 16), the curve is
produced with all inputs floating (OUT is low) and
indicates the lowest static I
configuration. For other states, additional current flows
through the 100k resistors on the inputs and outputs
shown in the block diagrams (see Figure 5 - Figure 6).
In these cases, the actual static I
obtained from the curves plus this additional current.
MillerDrive™ Gate Drive Technology
FAN3100
architecture shown in Figure 42 for the output stage, a
combination of bipolar and MOS devices capable of
providing large currents over a wide range of supply
voltage and temperature variations. The bipolar devices
carry the bulk of the current as OUT swings between 1/3
to 2/3 V
high or low rail.
The purpose of the MillerDrive™ architecture is to speed
up switching by providing the highest current during the
Miller plateau region when the gate-drain capacitance of
the MOSFET is being charged or discharged as part of
the
For applications that have zero voltage switching during
the MOSFET turn-on or turn-off interval, the driver
supplies high peak current for fast switching even
though the Miller plateau is not present. This situation
DD
DD
(static) typical performance graphs (Figure 9 -
and
DD
turn-on
and the MOS devices pull the output to the
. The CMOS input configuration offers a
drivers
there
DD
incorporate
level and, with V
is
/
a
DD
hysteresis
current for the tested
turn-off
DD
current is the value
the
DD
MillerDrive™
of 12V, the
voltage
process.
DD
. The
DD
DD
of
14
often occurs in synchronous rectifier applications
because the body diode is generally conducting before
the MOSFET is switched on.
The output pin slew rate is determined by V
and the load on the output. It is not user adjustable, but
if a slower rise or fall time at the MOSFET gate is
needed, a series resistor can be added.
Under-Voltage Lockout
The FAN3100 start-up logic is optimized to drive ground
referenced N-channel MOSFETs with a under-voltage
lockout (UVLO) function to ensure that the IC starts up
in an orderly fashion. When V
3.9V operational level, this circuit holds the output low,
regardless of the status of the input pins. After the part
is active, the supply voltage must drop 0.2V before the
part shuts down. This hysteresis helps prevent chatter
when low V
power switching. This configuration is not suitable for
driving high-side P-channel MOSFETs because the low
output voltage of the driver would turn the P-channel
MOSFET on with V
VDD Bypass Capacitor Guidelines
To enable this IC to turn a power device on quickly, a
local, high-frequency, bypass capacitor C
ESR and ESL should be connected between the VDD
and GND pins with minimal trace length. This capacitor
is in addition to bulk electrolytic capacitance of 10µF to
47µF often found on driver and controller bias circuits.
A typical criterion for choosing the value of C
keep the ripple voltage on the V
this is achieved with a value ≥ 20 times the equivalent
load capacitance C
Ceramic capacitors of 0.1µF to 1µF or larger are
common choices, as are dielectrics, such as X5R and
X7R, which have good temperature characteristics and
high pulse current capability.
If circuit noise affects normal operation, the value of
C
C
larger value, based on equivalent load capacitance, and
the other a smaller value, such as 1-10nF, mounted
BYP
BYP
Figure 42. MillerDrive™ Output Architecture
may be split into two capacitors. One should be a
may be increased to 50-100 times the C
DD
supply voltages have noise from the
DD
EQV
below 3.9V.
, defined here as Q
DD
is rising, yet below the
DD
supply ≤5%. Often
BYP
www.fairchildsemi.com
DD
with low
BYP
gate
voltage
EQV
/V
is to
, or
DD
.