TLE7230R Infineon Technologies, TLE7230R Datasheet - Page 10

• Manufacturer Part Number: TLE7230R
• Description: IC SW SMART OCTAL LOWSIDE PDSO36
• Manufacturer: Infineon Technologies
• Type: Low Sider

Specifications of TLE7230R

• Input Type: SPI
• Number Of Outputs: 8
• On-state Resistance: 800 mOhm
• Current - Peak Output: 2A
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 150°C
• Mounting Type: Surface Mount
• Package / Case: DSO-36
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Output / Channel: -
• Other names: SP000067170; SP000311685; TLE7230R; TLE7230RNT; TLE7230RT; TLE7230RT; TLE7230RTR; TLE7230RXT

Register Description:
Input Mapping Register (MAP)
Defines to which outputs the input IN4 is assigned (can be one up to all)
Boolean operation Register (BOL)
The logic operation for serial and parallel control signal can be individually defined for each channel.
Overload Behavior Register (OVL)
The overload behavior of individual channels can be defined.
Overtemperature Behavior Register (OVT)
The overtemperature behavior of individual channels can be defined
Switching Speed / Slew Rate Register (SLE)
The switching speed of individual channels can be defined.
Output State Register (STA)
Reads back the state of the output (this register is read-only)
Serial Output Control Register (CTL)
Sets the serial control bits for switching of output stages.
V3.4
Name
MAP
BOL
OVL
OVT
SLE
STA
CTL
Nr.
1
2
3
4
5
6
7
0.. No connection to IN4
1.. Output can be controlled with IN4 pin
0.. Logic "OR"
1.. Logic "AND"
0.. Current limit without shutdown of the channel
1.. Current limit with latching overload shutdown of the channel
0.. Auto restart after cooling down
1.. Latching shutdown on overtemperature
0.. fast (10µs)
1.. slow (50µs)
0: DMOS off
1: DMOS on
0: Output off
1: Output on
OUT8
Ch8
Ch8
Ch8
Ch8
Ch8
Ch8
7
OUT7
Ch7
Ch7
Ch7
Ch7
Ch7
Ch7
6
OUT6
Ch6
Ch6
Ch6
Ch6
Ch6
Ch6
5
OUT5
Ch5
Ch5
Ch5
Ch5
Ch5
Ch5
4
Page
OUT4
Ch4
Ch4
Ch4
Ch4
Ch4
Ch4
3
10
D a t a S h e e t T L E 7 2 3 0 R
OUT3
Ch3
Ch3
Ch3
Ch3
Ch3
Ch3
2
OUT2
Ch2
Ch2
Ch2
Ch2
Ch2
Ch2
1
OUT1
Ch1
Ch1
Ch1
Ch1
Ch1
Ch1
0
ADDR
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
2009-07-15
default
08
00
00
00
00
00
00
H
H
H
H
H
H
H