TLE7209-2R Infineon Technologies, TLE7209-2R Datasheet - Page 11

• Manufacturer Part Number: TLE7209-2R
• Description: IC H-BRIDGE 7A DC MOTOR PDSO-20
• Manufacturer: Infineon Technologies
• Type: Half Bridge DC Motor Driverr

Specifications of TLE7209-2R

• Applications: DC Motor Controller, Stepper Motor Controller
• Number Of Outputs: 1
• Current - Output: 5A
• Voltage - Supply: 5 V ~ 28 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: DSO-20
• Operating Supply Voltage: 5 V to 28 V
• Supply Current: 30 mA
• Mounting Style: SMD/SMT
• Packages: PG-DSO-20
• Current Limit (min.): 5.5 A
• Rthjc (max): 1.5 K/W
• Quiescent Current (max.): 20mA
• Operating Range: 5 - 28 V
• Rds (on) (typ./switch): 150.0 mOhm
• For Use With: DEMOBOARDTLE7209-2RIN - BOARD DEMO FOR TLE 7209-2R
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Load: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: SP000014748; SP000294312; TLE72092RNT; TLE72092RT; TLE72092RXT

6. Because only read access is used in the TLE 7209-2R, the SDI data-bits (2nd byte)
7. Invalid instruction/access:
8. Transfer error bit TRANS_F:
Final Datasheet
are not used
An instruction is invalid if an unused instruction code is detected (see tables with SPI
instructions). In case an unused instruction code occurred, the data byte “ff
error) will be transmitted after having sent the verification byte. This transmission
takes place within the same SPI-frame that contained the unused instruction byte. In
addition any transmission is invalid if the number of SPI clock pulses (falling edge)
counted during active CSN differs from exactly 16 clock pulses. If an invalid instruction
is detected, bit TRANS_F in the following verification byte (next SPI transmission) is
set to HIGH. The TRANS_F bit must not be cleared before it has been sent to the
microcontroller.
The bit TRANS_F indicates an error during the previous transfer. An error is
considered to have occurred when an invalid command was sent, the number of SPI
clock pulses (falling edge) counted during active CSN was less than or greater than
16 clock pulses, or SPI clock (SCK) was logical high during falling edge of CSN.
11
Circuit Description
V1.3, 2005-jan-11
TLE 7209-2R
hex
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