TLE7810G Infineon Technologies, TLE7810G Datasheet - Page 27

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TLE7810G

Manufacturer Part Number
TLE7810G
Description
IC LDO VREG/LIN TXRX DSO-28
Manufacturer
Infineon Technologies
Datasheet

Specifications of TLE7810G

Applications
Special Purpose
Voltage - Supply
3.9 V ~ 27 V
Operating Temperature
-40°C ~ 150°C
Mounting Type
Surface Mount
Package / Case
DSO-28
Data Bus Width
8 bit
Program Memory Type
Flash
Program Memory Size
16 KB
Data Ram Size
768 B
Interface Type
SPI, SSC, UART
Maximum Clock Frequency
4 MHz
Number Of Timers
3
Maximum Operating Temperature
+ 150 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Current - Supply
-
Lead Free Status / Rohs Status
 Details
Other names
SP000313890

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
TLE7810G
Manufacturer:
INFINEON/英飞凌
Quantity:
20 000
Company:
Part Number:
TLE7810G
Quantity:
4 800
10
In addition to a wake-up from SBC Stop / Sleep Mode via the LIN bus line it is also possible to wake-up the
TLE7810G from low power mode via the monitoring/wake-up inputs. These inputs are sensitive to a transition of
the voltage level, either from high to low or vice versa. Monitoring is available in Active Mode and indicates the
voltage level of the inputs via SPI status bits.
A positive or negative voltage edge at MONx in SBC Sleep or Stop Mode results in signalling a wake-up event (via
SBC [DO] to μC [P1.4] interconnect). After a wake-up via MONx the first transmission of the SPI diagnosis word
in SBC Standby mode indicates the wake-up source. Further SPI status word transmissions show the logic level
at the monitoring input pins.
Note: Immediately before switching the TLE7810G into a SBC power saving mode the activated MONx are
The monitoring input module consists of an input circuit with pull-up and pull-down current sources to define a
certain voltage level with open inputs and a filter function to avoid wake-up events caused by unwanted voltage
transients at the module inputs.
At a voltage level at the monitoring pins of
while at 1 V <
monitoring/wake-up inputs. Below and above these voltage ranges the current is minimized to a leakage current
(see
Figure 11
Data Sheet
“Monitoring Inputs MONx” on Page
initialized with the actual logic level detected at the MONx. In case a MONx is deactivated it can neither be
used as wake-up source nor can it be used to detect logic levels.
However, there should be a minimum delay of three times “CSN high time” (see
Timing1)” on Page
MONx
Monitoring / Wake-Up Inputs MON1 … 5 and Wake-Up Event
Signalling
Monitoring Input Block Diagram
V
MONx
<
V
MON_th
43) between activation of MONx and entering a power saving mode.
the pull-down sink is activated (see
Vs
Monitoring / Wake-Up Inputs MON1 … 5 and Wake-Up Event Signalling
38).
V
1
MON_th
<
V
+
27
-
MONx
< 5.5 V the pull-up current source becomes active,
Figure
11) guaranteeing stable levels at the
t
Table “SPI Data Input
WK
Rev. 3.01, 2008-04-15
TLE7810G

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