XCCACE128-I Xilinx Inc, XCCACE128-I Datasheet - Page 35

• Manufacturer Part Number: XCCACE128-I
• Description: IC 128MBIT ACE FLASH CARD
• Manufacturer: Xilinx Inc

Specifications of XCCACE128-I

• Memory Size: 128Mb
• Memory Type: FLASH
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

The JTAG signals are directly multiplexed from the respective configuration source. The TSTJTAG logic is connected to the
CFGJTAG port as long as the CompactFlash and MPU interfaces are not connected to the CFGJTAG port. Outlined in the
following sections are the details of the JTAG interface for the System ACE CF controller.
The available Boundary-Scan registers for the System ACE CF controller are shown in
Table 21: System ACE CF Controller Boundary-Scan Registers
Instruction Register
The Instruction Register (IR) for the System ACE CF controller is eight bits wide and is connected between TDI and TDO
during an instruction scan sequence. The Instruction Register is parallel loaded with a fixed instruction capture pattern in
preparation for an instruction sequence. This pattern is shifted out onto TDO (LSB first), while an instruction is shifted into
the instruction register from TDI. This pattern is illustrated in
Table 22: Instruction Register Values Loaded into IR During Instruction Scan Sequence
The optional IDCODE instruction is supported in addition to the mandatory instructions (BYPASS, SAMPLE/PRELOAD, and
EXTEST). The binary values for these instructions are listed in
DS080 (v2.0) October 1, 2008
Product Specification
Instruction Register
Boundary-Scan Register
Identification Register
Bypass Register
CFGINSTRERR
(MPU ERRORREG
register bit)
Register Name
IR[7]
R
CFGDATA (from core)
CFGSEL (from core)
CFGFAILED
(MPU ERRORREG
register bit)
IR[6]
TSTTMS
TSTTCK
CFGTDI
Register Length
TSTTDI
109 bits
32 bits
8 bits
1 bit
Figure 16: Test JTAG Interface Block Diagram
CFGREADERR
(MPU ERRORREG
register bit)
IR[5]
Holds current instruction OPCODE and captures internal device status.
Controls and observes input, output, and output enable.
Captures device IDCODE.
Device bypass.
Boundary Scan Register
Identifcation Register
Instruction Register
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Bypass Register
Controller
Table
CFCERROR
(MPU STATUSREG
register bit)
Logic
TAP
Figure 23, page
22.
IR[4]
Description
36.
CFGERROR
(MPU STATUSREG
register bit)
System ACE CompactFlash Solution
Table
IR[3]
1
0
21.
DS080_45_030801
CFGTDO
TSTTDO
CFGTCK
CFGTMS
CFGDONE
IR[2]
01
IR[1:0]
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